74AUP1G175GW,125 NXP Semiconductors, 74AUP1G175GW,125 Datasheet - Page 13
![IC D F-F POS-EDGE TRIG SC-88](/photos/5/31/53138/568-umt6_sot-363_sc-88__sot363_sml.jpg)
74AUP1G175GW,125
Manufacturer Part Number
74AUP1G175GW,125
Description
IC D F-F POS-EDGE TRIG SC-88
Manufacturer
NXP Semiconductors
Series
74AUPr
Type
D-Typer
Datasheet
1.74AUP1G175GM115.pdf
(23 pages)
Specifications of 74AUP1G175GW,125
Output Type
Non-Inverted
Package / Case
SC-70-6, SC-88, SOT-363
Function
Master Reset
Number Of Elements
1
Number Of Bits Per Element
1
Frequency - Clock
50MHz
Delay Time - Propagation
21.1ns
Trigger Type
Positive Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
AUP
Logic Type
CMOS
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
19.5 ns
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
0.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP1G175GW-G
74AUP1G175GW-G
935280003125
74AUP1G175GW-G
935280003125
NXP Semiconductors
12. Waveforms
Table 9.
74AUP1G175
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Fig 7.
Fig 8.
CC
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to
D hold times and the maximum input clock frequency
Measurement points are given in
V
CP recovery time
The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to
OL
OL
Measurement points
and V
and V
OH
OH
are typical output voltage drop that occur with the output load.
are typical output voltage drop that occur with the output load.
MR input
CP input
Q output
CP input
Q output
D input
Output
V
0.5 × V
M
GND
GND
GND
GND
V
V
V
V
CC
OH
OH
OL
OL
V
V
V
V
I
I
Table
I
I
Table
All information provided in this document is subject to legal disclaimers.
9.
9.
Rev. 3 — 30 September 2010
V
M
t
su
Low-power D-type flip-flop with reset; positive-edge trigger
Input
V
0.5 × V
M
t
V
V
h
M
M
CC
t
V
PHL
t
W
M
t
PHL
t
W
1/f
max
V
M
t
su
V
V
t
rec
I
CC
t
V
h
M
001aaa464
001aaa465
t
PLH
74AUP1G175
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
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