74HC173D,653 NXP Semiconductors, 74HC173D,653 Datasheet - Page 10
![IC QUAD D F-F POS-EDGE 16SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
74HC173D,653
Manufacturer Part Number
74HC173D,653
Description
IC QUAD D F-F POS-EDGE 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Type
D-Type Busr
Datasheet
1.74HCT173DB112.pdf
(10 pages)
Specifications of 74HC173D,653
Output Type
Tri-State Non Inverted
Package / Case
16-SOIC (3.9mm Width)
Function
Master Reset
Number Of Elements
1
Number Of Bits Per Element
4
Frequency - Clock
95MHz
Delay Time - Propagation
16ns
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
HC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
17 ns at 5 V
High Level Output Current
- 7.8 mA
Low Level Output Current
7.8 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Technology
CMOS
Number Of Bits
4
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
5V
Package Type
SO
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4558-2
74HC173D-T
74HC173D-T
933714560653
74HC173D-T
74HC173D-T
933714560653
Philips Semiconductors
AC WAVEFORMS
December 1990
Quad D-type flip-flop; positive-edge trigger;
3-state
(1) HC : V
Fig.6
(1) HC : V
Fig.8
HCT: V
HCT: V
Waveforms showing the clock (CP) to
output (Q
pulse width, the output transition times and
the maximum clock pulse frequency.
Waveforms showing the 3-state enable and
disable times.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
n
I
I
I
) propagation delays, the clock
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
10
PACKAGE OUTLINES
See
(1) HC : V
Fig.7
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
Fig.9 Waveforms showing the data set-up and hold
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
HCT: V
HCT: V
times from input (En, D
Waveforms showing the master reset (MR)
pulse width, the master reset to output (Q
propagation delays and the master reset to
clock (CP) removal time.
M
M
M
M
= 50%; V
= 1.3 V; V
= 50%; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
n
74HC/HCT173
) to clock (CP).
Product specification
n
)
.