74LVC374AD,112 NXP Semiconductors, 74LVC374AD,112 Datasheet - Page 2

• Manufacturer Part Number: 74LVC374AD,112
• Description: IC OCT D FF POS-EDG TRIG 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC374AD,112

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 80MHz
• Delay Time - Propagation: 1.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVC374AD; 74LVC374AD; 935218660112

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 May 14
t
f
C
C
PHL
max
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state
P
f
f
C
V
N = total load switching outputs;
SYMBOL
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
2
V
CC
= 25 C; t
f
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per gate V
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
CC
r
= t
= 0 V
f
PARAMETER
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
2
C
DESCRIPTION
The 74LVC374A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC374A is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus-oriented applications. A clock input (CP)
and an outputs enable input (OE) are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is
available at the outputs. When pin OE is HIGH, the outputs
go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
The 74LVC374A is functionally identical to the
74LVC574A, but the 74LVC574A has a different pin
arrangement.
CC
L
D
= 50 pF; V
in W).
= 3.3 V; notes 1 and 2
CONDITIONS
CC
= 3.3 V
2.7
100
4.0
15
TYPICAL
Product specification
74LVC374A
ns
MHz
pF
pF
UNIT