74LVC374ADB,118 NXP Semiconductors, 74LVC374ADB,118 Datasheet - Page 9

• Manufacturer Part Number: 74LVC374ADB,118
• Description: IC OCT D FF POS-EDG TRIG 20SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC374ADB,118

• Package / Case: 20-SSOP
• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 80MHz
• Delay Time - Propagation: 1.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 2.7 ns at 3.3 V
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: SSOP
• Low Level Output Current: 24mA
• Frequency (max): 80MHz
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC374ADB-T; 74LVC374ADB-T; 935218670118

Philips Semiconductors
AC CHARACTERISTICS
GND = 0 V; t
2003 May 14
T
t
t
t
t
t
t
f
t
SYMBOL
PHL
PZH
PHZ
W
su
h
max
sk(0)
amb
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state
/t
/t
/t
PLH
PZL
PLZ
= 40 to +85 C; note1
r
propagation delay CP to Qn
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
clock pulse width HIGH or LOW
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
= t
f
2.5 ns; C
PARAMETER
L
= 50 pF; R
L
= 500 .
Figs 7 and 10
Figs 8 and 10
Figs 8 and 10
Fig.7
Fig.9
Fig.9
Fig.7
note 2
WAVEFORM
TEST CONDITIONS
9
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
3.0 to 3.6
V
CC
(V)
1.5
1.5
1.5
1.5
1.5
1.5
3.0
3.0
2.0
2.0
1.5
1.5
80
100
MIN.
16
2.9
2.7
19
4.1
3.4
8.0
2.7
2.4
1.5
0
0.6
TYP.
Product specification
74LVC374A
8.0
7.0
8.5
7.5
7.0
6.0
1.0
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
UNIT