upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet - Page 13

• Manufacturer Part Number: upd44645182af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 2-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

Bus Cycle State Diagram
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
W# = LOW
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
WRITE PORT NOP
Always
WRITE DOUBLE
WRITE ADDRESS
LOAD NEW
AT K#
AT K#
W# = HIGH
W# = HIGH
W# = LOW
Supply voltage
Preliminary Data Sheet M19958EJ1V0DS
provided
μ
PD44645092A-A, 44645182A-A, 44645362A-A
Power UP
Supply voltage
provided
R# = LOW
READ PORT NOP
READ ADDRESS
READ DOUBLE
LOAD NEW
R_Init = 0
R# = HIGH
Always
R# = HIGH
R# = LOW
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