upd44645184af5-fq1-a Renesas Electronics Corporation., upd44645184af5-fq1-a Datasheet - Page 6

• Manufacturer Part Number: upd44645184af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 4-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

Pin Identification
6
A
D0 to Dxx
Q0 to Qxx
R#
W#
BWx#
K, K#
C, C#
Symbol
Input
Input
Output
Input
Input
Input
Input
Input
Type
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of four words (two clock
periods of bus activity). These inputs are ignored when device is deselected, i.e., NOP (R# =
W# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. See Pin Configurations for ball site location of individual
signals.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and
K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and C# (or
K and K#), depending on the R# command. See Pin Configurations for ball site location of
individual signals.
Synchronous Read: When LOW this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising edge of
K. If a READ command (R# = LOW) is input, an input of R# on the subsequent rising edge of K
is ignored.
Synchronous Write: When LOW this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge
of K. If a WRITE command (W# = LOW) is input, an input of W# on the subsequent rising edge
of K is ignored.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered
and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first and third output data. The
rising edge of C is used as the output reference for second and fourth output data. Ideally, C# is
180 degrees out of phase with C. When use of K and K# as the reference instead of C and C#,
then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to
HIGH (i.e. toggle of C and C#).
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
Preliminary Data Sheet M19959EJ1V0DS
μ
PD44645094A-A, 44645184A-A, 44645364A-A
Description
(1/2)