upd44645184af5-fq1-a Renesas Electronics Corporation., upd44645184af5-fq1-a Datasheet - Page 13

• Manufacturer Part Number: upd44645184af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 4-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

Bus Cycle State Diagram
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
W# = LOW
R_Init = 0
2. Read and write state machines can be active simultaneously.
3. State machine control timing is controlled by K.
W# = HIGH
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
Read and write cannot be simultaneously initiated. Read takes precedence.
W_Count = 2
W_Count = W_Count+2
WRITE PORT NOP
INCREMENT WRITE
ADDRESS BY TWO
WRITE DOUBLE;
Always
WRITE ADDRESS;
W_Count = 0
LOAD NEW
Always
W# = LOW & W_Count = 4
Supply voltage
Preliminary Data Sheet M19959EJ1V0DS
provided
& W_Count = 4
W# = HIGH
μ
PD44645094A-A, 44645184A-A, 44645364A-A
Power UP
& R_Count = 4
R# = HIGH
R# = LOW & R_Count = 4
Supply voltage
provided
R_Count = 2
R_Count = R_Count+2
ADDRESS BY TWO
READ ADDRESS;
INCREMENT READ
READ PORT NOP
READ DOUBLE;
R_Count = 0;
LOAD NEW
R_Init = 1
R_Init = 0
R_Init = 0
Always
Always
R# = HIGH
R# = LOW
13