ds1861 Maxim Integrated Products, Inc., ds1861 Datasheet - Page 22

• Manufacturer Part Number: ds1861
• Description: Ds1861 Full Laser Control With Fault Management
• Manufacturer: Maxim Integrated Products, Inc.

Full Laser Control with Fault Management
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave returns control of
SDA to the master.
Slave Address Byte: Each slave on the I
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte
(Figure 15) contains the slave address in the most sig-
nificant 7 bits and the
The DS1861’s slave address is 1010A
where A
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W = 0, the master indi-
cates it will write data to the slave. If R/W = 1, the mas-
ter will read data from the slave. If an incorrect slave
address is written, the DS1861 assumes the master is
communicating with another I
communications until the next start condition is sent.
Memory Address: During an I
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes and gener-
ates a stop condition.
22
____________________________________________________________________
2
, A
1
, and A
R/W bit in the least significant bit.
0
are the values of the address
2
I
C device and ignore the
2
2
C Communication
C write operation, the
2
A
1
A
0
(binary),
2
C bus
The DS1861 can write 1 to 8 bytes (referred to as 1
row) with a single write transaction. This is internally
controlled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one row of the mem-
ory map. Attempts to write to additional memory rows
without sending a stop condition between rows will
result in the address counter wrapping around to the
beginning address of the present row.
Example: A 3-byte write starts at address BEh and writes
three data bytes (11h, 22h, and 33h) to three “consecu-
tive” addresses. The result would be addresses BEh and
BFh would contain 11h and 22h, respectively, and the
third data byte, 33h, would be written to address B8h.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the row,
and then wait for the bus free or EEPROM write time to
elapse. Then the master can generate a new start con-
dition, write the slave address byte (R/W = 0), and the
first memory address of the next memory row before
continuing to write data.
Acknowledge Polling: Any time EEPROM is written,
the DS1861 requires the EEPROM write time (t
the stop condition to write the contents of the row to
EEPROM. During the EEPROM write time, the DS1861
does not acknowledge its slave address because it is
busy. It is possible to take advantage of this phenome-
non by repeatedly addressing the DS1861, which
allows the next row to be written as soon as the DS1861
is ready to receive the data. The alternative to acknowl-
edge polling is to wait for maximum period of t
elapse before attempting to write again to the DS1861.
EEPROM Write Cycles: When EEPROM writes occur,
the DS1861 will write the whole EEPROM memory row
even if only a single byte on the row was modified.
Writes that do not modify all 8 bytes on the row are
allowed and do not corrupt the remaining bytes of
memory on the same row. Because the whole row is
written, bytes on the row that were not modified during
the transaction are still subject to a write cycle. This
Figure 15. Slave Address Byte
SIGNIFICANT BIT
MOST
1
7-BIT SLAVE ADDRESS
0
1
0 A
A
PIN VALUES
2
, A
2
1
A
AND A
1
A
0
0
R/W
READ OR WRITE
DETERMINES
W
) after
W
to