ds1865 Maxim Integrated Products, Inc., ds1865 Datasheet - Page 15

• Manufacturer Part Number: ds1865
• Description: Pon Triplexer Control And Monitoring Circuit Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

inadequate V
adequate V
outputs are enabled following the same sequence as the
power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOSFET or
pMOSFET. This requires that the FETG output can sink
or source current. Because the DS1865 does not know
if it should sink or source current before V
V
be high impedance when V
Low-Voltage Operation section for details and
diagram). The application circuit must use a pullup or
pulldown resistor on this pin that pulls FETG to the
alarm/shutdown state (high for a pMOS, low for a
nMOS). Once V
FETG output to the state determined by the FETG DIR
bit (Table 02h, Register 89h). FETG DIR is 0 if an nMOS
is used and 1 if a pMOS is used.
Table 4. TX-F as a Function of TX-D and
Alarm Sources
Figure 5. TX-F Timing
POA
V
CC
Yes
Yes
Yes
, which triggers the EE recall, this output will
> V
No
POA
CC
CC
is present to clear the V
CC
exists to operate the laser driver. Once
TX-D
is above V
X
0
0
1
CC
NONMASKED
TX-F ALARM
DETECTION OF
DETECTION OF
POA
TX-F FAULT
TX-F RESET
TX-F FAULT
is below V
TX-D OR
, the DS1865 pulls the
TX-F NON LATCHED OPERATION
TX-F LATCHED OPERATION
X
X
0
1
TX-F
TX-F
____________________________________________________________________
CC
low alarm, the
POA
CC
exceeds
(see the
TX-F
1
0
1
0
PON Triplexer Control and
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1865’s Alarm Trap
Bytes (ATB) through the I
ATB has a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1865 sets the
corresponding bit in the ATB. Active ATB bits remain set
until written to zeros through the I
up, the ATB is zeros until alarms dictate otherwise.
The DS1865 has an ID hard coded to its die. Two regis-
ters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h reads 65h to identify the part as the
DS1865, byte 87h reads the die revision.
The DS1865 contains two power-on reset (POR) levels.
The lower level is a digital POR (V
level is an analog POR (V
supply voltage rises above V
abled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM), and all analog circuitry is dis-
abled. When V
and the analog circuitry is enabled. While V
above V
and it responds based on its nonvolatile configuration.
If during operation V
above V
POA
POD
Monitoring Circuit
, the device is in its normal operating state,
, the SRAM retains the SEE settings from
CC
reaches V
Determining Alarm Causes
CC
2
Using the I
C interface (in Table 01h). The
Low-Voltage Operation
falls below V
POA
POA
POA
). At startup, before the
2
Die Identification
C interface. On power-
, the SEE is recalled,
, the outputs are dis-
POD
) and the higher
2
POA
C Interface
CC
but is still
remains
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