ds1865 Maxim Integrated Products, Inc., ds1865 Datasheet - Page 14

• Manufacturer Part Number: ds1865
• Description: Pon Triplexer Control And Monitoring Circuit Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

PON Triplexer Control and
Monitoring Circuit
The ADC results (after right shifting, if used) are com-
pared to high alarm thresholds, low alarm thresholds,
and the warning threshold after each conversion, and
the corresponding alarms are set, which can be used
to trigger the TX-F or FETG outputs. These ADC thresh-
olds are user programmable, as are the masking regis-
ters that can be used to prevent the alarms from
triggering the TX-F and FETG outputs.
There are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4. The
total time required to convert all six channels is t
Timing Characteristics (Control Loop and Quick-Trip)
for details).
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale value defined by a
standard’s specification, then right shifting can be used
to adjust the predetermined full-scale analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1865’s range is wide enough to cover all
requirements; when the maximum input value is far
short of the FS value, right shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8th the specified predetermined full-
scale value, so only 1/8th the converter’s range is used.
An alternative is to calibrate the ADC’s full-scale range
to 1/8th the readable predetermined full-scale value
and use a right-shift value of 3. With this implementa-
tion, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of Right Shift Control registers
(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four ana-
log channels, MON1–MON4, each have 3 bits allocated
to set the number of right shifts. Up to 7 right-shift oper-
14
Figure 4. ADC Round-Robin Timing
NOTE: AT POWER-UP, IF THE V
TIMING CYCLES BETWEEN TEMP AND V
____________________________________________________________________
CC
LOW ALARM IS SET FOR EITHER THE TX-F OR FETG OUTPUT, THE ADC ROUND-ROBIN
CC
ONLY UNTIL V
Right Shifting ADC Result
MON4
CC
ONE ROUND-ROBIN ADC CYCLE
IS ABOVE THE V
TEMP
ADC Timing
CC
VCC
LOW THRESHOLD.
RR
(see
MON1
t
RR
ations are allowed and are executed as a part of every
conversion before the results are compared to the high
and low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
62h–6Bh). This is true during the setup of internal cali-
bration as well as during subsequent data conversions.
The TX-F output has masking registers for the six ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable through the TX-F mask to cause TX-F to
assert. All alarms, with the exception of FETG, only
cause TX-F to remain active while the alarm condition
persists. However, the TX-F latch bit can enable the TX-F
output to remain active until it is cleared by the TX-F
reset bit, TX-D, soft TX-D, or by power cycling the part. If
the FETG output is configured to trigger TX-F, it indicates
that the DS1865 is in shutdown, and requires TX-D, soft
TX-D, or cycling power to reset. The QT alarms are
masked until the completion of the binary search. Only
enabled alarms will activate TX-F. See Figure 5.
Table 4 shows TX-F as a function of TX-D and the alarm
sources.
The FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
the FETG output is always latched in case it is triggered
by an unmasked alarm condition. Its output polarity is
programmable to allow an external nMOSFET or
pMOSFET to open during alarms to shut off the laser
diode current. If the FETG output triggers, indicating that
the DS1865 is in shutdown, it requires TX-D, soft TX-D, or
cycling power to be reset. Under all conditions, when the
analog outputs are reinitialized after being disabled, all
the alarms with the exception of the V
are cleared. The V
prevent the output from attempting to operate when
MON2
MON3
MON4
Transmit Fault (TX-F) Output
CC
Safety Shutdown (FETG) Output
low alarm must remain active to
TEMP
VCC
CC
low ADC alarm