ds1859 Maxim Integrated Products, Inc., ds1859 Datasheet
ds1859
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ds1859 Summary of contents
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... Rev 4; 2/06 Dual, Temperature-Controlled Resistors with General Description The DS1859 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 50k or two 20k , 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-to-digital temperature sensor. The device provides an ideal method for setting and tem- perature-compensating bias voltages and currents in control applications using minimal circuitry ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors ABSOLUTE MAXIMUM RATINGS Voltage Range on V Relative to Ground ...........-0.5V to +6.0V CC Voltage Range on Inputs Relative to Ground* ................................................-0. Voltage Range on Resistor Inputs Relative to Ground* ................................................-0.5V ...
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Dual, Temperature-Controlled Resistors with ANALOG RESISTOR CHARACTERISTICS (V = 2.85V to 5.5V -40°C to +95°C, unless otherwise noted PARAMETER SYMBOL Position 00h Resistance (50k ) Position FFh Resistance (50k ) Position 00h Resistance (20k ) Position ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors AC ELECTRICAL CHARACTERISTICS (V = 2.85V to 5.5V -40°C to +95°C, unless otherwise noted. See Figure 6 PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between STOP and START ...
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Dual, Temperature-Controlled Resistors with Note 10: After this period, the first clock pulse is generated. Note 11: The maximum t only has to be met if the device does not stretch the LOW period (t HD:DAT Note 12: A device ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors (V = 5.0V +25°C, for both 50k and 20k versions, unless otherwise noted RESISTOR 0 DNL (LSB) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 ...
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Dual, Temperature-Controlled Resistors with (V = 5.0V +25°C, for both 50k and 20k versions, unless otherwise noted POSITION 00h RESISTANCE vs. TEMPERATURE 0.38 20k VERSION 0.37 0.36 0.35 0.34 0.33 -40 -25 - ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors PIN BALL NAME 1 B2 SDA 2-Wire Serial Data I/O Pin. Transfers serial data to and from the device SCL 2-Wire Serial Clock Input. Clocks data into and out of the ...
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... SRAM MINT (BIT BIT TxF 60h-7Fh NOT PROTECTED TABLE SELECT MEASUREMENT WARNING FLAGS ALARM FLAGS RIGHT SHIFTING INTERNAL DS1859 ADC 12-BIT MONITORS LIMIT HIGH A/D CTRL MONITORS LIMIT LOW MEASUREMENT PROT AUX COMPARATOR COMP CTRL PROT MAIN WARNING FLAGS ALARM FLAGS ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Table 1. Scales for Monitor Channels at Factory Setting +FS +FS SIGNAL SIGNAL (hex) Temperature 127.984 C 7FFC V 6.5528V FFF8 CC MON1 2.4997V FFF8 MON2 2.4997V FFF8 MON3 2.4997V FFF8 Table 2. ...
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Dual, Temperature-Controlled Resistors with Table 4. ADEN Address Configuration ADEN NO. OF SEPARATE (ADDRESS DEVICE ENABLE) ADDRESSES (Main Device only) MAIN DEVICE ENABLE AUXILIARY DEVICE ENABLE DEC 127 128 143 199 Figure 2. ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors MAIN DEVICE ENABLE DEC 127 128 143 199 255 Figure 3. Memory Organization, ADEN = 1 above is accessible only through the Main Device address. This memory is organized as ...
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Dual, Temperature-Controlled Resistors with A description of the registers is below. The registers are read only (R) or read/write (R/W). The R/W registers are writable only if write protect has not been asserted (see the Memory Description section). Auxiliary Device ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex EEPROM R EEPROM R EEPROM R EEPROM R EEPROM ...
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Dual, Temperature-Controlled Resistors with Main Device (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex SRAM SRAM — 6E SRAM — Bit 7 — 6 — R/W 5 — — 4 — — 3 — — ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex) 4 — R/W 3 — — 2 — — 1 — — 0 — — 70 SRAM R Bit 7 — — 6 — ...
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Dual, Temperature-Controlled Resistors with Main Device (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex) 3 — — 2 — — 1 — — 0 — — SRAM — 74 SRAM Bit 7 — — 6 — — 5 ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex) 75 SRAM R Bit 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 — ...
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Dual, Temperature-Controlled Resistors with Table 01h MEMORY EEPROM/ LOCATION R/W SRAM (hex) 80 SRAM R/W Bit 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 — — 0 — — ...
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Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Table 01h (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex) 5 — — 4 — — 3 — — 2 — — 1 — — 0 — — EEPROM — 8C ...
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Dual, Temperature-Controlled Resistors with Table 01h (continued) MEMORY EEPROM/ LOCATION R/W SRAM (hex EEPROM — EEPROM R EEPROM R EEPROM R EEPROM R ...
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... Instead they have a circuit that transforms light, fre- 10E-9 quency, power, or current to a voltage that is the input — to the DS1859. In this situation, the user does not need to know the relationship of voltage to expected digital result but instead knows the relationship of light, fre- quency, power, or current to the expected digital result. ...
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... The gain register is now set and the resolution of the conversion will best match the expected LSB. The next step is to calibrate the offset of the DS1859. With the correct gain value written to the gain register, again force the null input to the pin. Read the digital result from the part (Meas1) ...
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... See the timing diagrams in Figures 5 and 6 for further details. STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition. After a read or write sequence, the stop command places the DS1859 into a low-power mode. See the timing diagrams in Figures 5 . Temperature frame and 6 for further details ...
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... EEPROM memory. All inputs are dis- w abled during this byte write cycle. The DS1859 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. For example, addresses 00h through 07h constitute one page ...
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... Once the device address is clocked in and acknowl- edged by the DS1859 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a STOP condition afterwards ...
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... Within the bus specifications, a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1859 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowl- edge bit ...
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... DS1859B-050/T&R 50k DS1859E-020 20k DS1859E-020+ 20k DS1859E-020/T&R 20k DS1859E-020+T&R 20k DS1859E-050 50k DS1859E-050+ 50k DS1859E-050+T&R 50k DS1859E-050/T&R 50k +Denotes lead-free package. T&R denotes tape-and-reel package. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...