ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 257
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 257 of 265
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Figure 36-8. Receive-Side Timing
Note 1: RSYNC is in the output mode.
Note 2: Shown is RLINK/RLCLK in the ESF framing mode.
Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied.
Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register.
RSER / RDATA / RSIG
RFSYNC / RMSYNC
RLINK (E1 MODE)
RLINK (T1MODE)
RCHCLK
RCHBLK
RSYNC
RLCLK
RCLK
2
1
4
t D1
t D2
t D1
Bit Position
Sa4 to Sa8
t D2
t D2
t D2
t D2
257 of 265
1ST FRAME BIT
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