ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 228
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 228 of 265
- Download datasheet (2Mb)
Figure 33-2. TAP Controller State Diagram
33.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI
and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage
toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with
JTMS HIGH moves the controller to the Update-IR state. The falling edge of that same JTCLK latches
the data in the instruction shift register to the instruction parallel output. Instructions supported by the
DS2156 and its respective operational binary codes are shown in Table 16-A.
1
0
Test Logic
Reset
Run Test/
Idle
0
1
0
1
Capture DR
Update DR
Pause DR
1
Select
DR-Scan
Exit2 DR
Shift DR
Exit DR
228 of 265
0
1
0
0
1
0
1
1
0
0
1
0
1
Capture IR
Update IR
1
Pause IR
Select
IR-Scan
Shift IR
Exit2 IR
Exit IR
0
1
1
1
0
0
0
1
1
0
0
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