ds2149qt-r Maxim Integrated Products, Inc., ds2149qt-r Datasheet - Page 7

• Manufacturer Part Number: ds2149qt-r
• Description: Ds2149 5v T1/j1 Line Interface Unit
• Manufacturer: Maxim Integrated Products, Inc.

PIN
Table 2-C. Signal Descriptions
13/
10
11
12
16
14
15
1
2
3
4
5
6
7
8
9
INSLER
INSBPV
TDATA
MODE1
RDATA
MODE0
NAME
TRING
MCLK
JASEL
TVDD
TNEG
RNEG
RCLK
TCLK
TPOS
RPOS
TTIP/
VSM
BPV
RCL
QPD
VSS
I/O
—
—
O
O
O
O
O
I
I
I
I
I
I
I
I
2
2
2
Master Clock. A 1.544MHz clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation.
Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit
side formatter. Can be sourced internally by MCLK or RCLK.
Transmit Positive Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line.
Transmit NRZ Data. Sampled on the falling edge of TCLK for data to be transmitted
onto the line.
Transmit Insert Logic Error. Rising edge on INSLER inserts a logic error into the
outbound QRSS pattern. Sampled on falling edge of TCLK.
Transmit Negative Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line.
Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK.
Rising edge inserts one BPV.
Mode Select 1. Connect low to select hardware mode. Connect high to select serial
port mode. See also MODE0.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge
(CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Always valid
on rising edge of RCLK in hardware mode.
Receive Bipolar Violation. Transitions high for one clock cycle marking an inbound
bipolar violation. Valid on rising edge of RCLK.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge
(CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Always valid on
rising edge of RCLK in hardware mode.
Receive Data. RDATA is the NRZ output from the line interface. Set NRZE
(CCR1.6) to a 1 for NRZ applications. In NRZ mode, data is output on RPOS while a
received error causes a positive-going pulse synchronous with RCLK at RNEG
(Section 6).
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in
absence of signal at RTIP and RRING.
Mode Select 0. Set high to disable all output pins (including the serial control port).
Set low for normal operation. Useful in board level testing. See also MODE1.
Voltage Supply Mode. Connect high for 5V operation. Has 10kW pullup.
Jitter Attenuator Select
0 = Place the jitter attenuator on the transmit side
1 = Place the jitter attenuator on the receive side
Float = Disable jitter attenuator
Not used in software mode
Receive Carrier Loss. An output that toggles high during a receive carrier loss.
QPD. Output high when QRSS detector is searching for QRSS data pattern. Output
high for one-half clock cycle on bit error. Connect to external counter to count bit
errors.
Transmit Tip and Ring. Analog line driver outputs. These pins connect through a
step-up transformer to the line (Section 5).
Ground for Transmitter Block
Positive Supply. 5.0V ±5% for the transmitter block. See also VSM pin 10.
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FUNCTION
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