ds2149qt-r Maxim Integrated Products, Inc., ds2149qt-r Datasheet - Page 21

• Manufacturer Part Number: ds2149qt-r
• Description: Ds2149 5v T1/j1 Line Interface Unit
• Manufacturer: Maxim Integrated Products, Inc.

Figure 10-1. Loopbacks in the DS2149 Block Diagram
10.2 Internal Pattern Generation and Detection
10.2.1 Transmit Alarm-Indication Signal (TAIS)
When TAIS is enabled (set TAIS in CR2, or pulling the TAIS pin high), the transmitter inputs
TPOS/TNEG and TDATA are ignored and the devices transmits unframed all ones at the transmitter
outputs at the TCLK frequency. If TCLK is not present, then the device uses MCLK to transmit. Both
TAIS and LLB can be enabled at the same time. The transmitter input data is looped back to the receiver
outputs through the jitter attenuator if enabled and the unframed all ones pattern is transmitted at TTIP
and TRING.
10.2.2 Quasirandom Signal Source (QRSS)
The QRSS data pattern is described in AT&T 62411. The pattern is represented by the polynomial 2
with the additional requirement that no more than 14 consecutive 0s be present in the pattern. When
QRSS is enabled (PAT0 = 0 and PAT1 = 1 in CR2 or float the QRSS pin), the data at the transmitter
inputs TPOS/TNEG or TDATA is ignored and replaced by the output of the QRSS pattern generator. In
addition, logic errors can be inserted into the data pattern with a rising edge on the INSLER input pin. If
no logic errors are to be inserted, then the INSLER pin must remain low. If the logic error occurs on the
same clock cycle as a 1 that has been inserted to suppress 15 0s, then the logic error is delayed until the
next clock cycle. The logic error insertion is available in both NRZ and bipolar data modes. Enabling the
QRSS pattern also enables the QRSS detector in the receiver. Pattern synchronization occurs when there
are no errors in 64 bits. When synchronized, the QPD output pin goes low. Once synchronized, an error
in the pattern causes the QPD output to go high for one-half RCLK cycle. In software mode, the level on
the CLKE pin determines the relationship between QPD and RCLK. When CLKE is low, QPD is high
when RCLK is high. When CLKE is high, QPD is high when RCLK is low. The QPD output can be used
to trigger an external bit error counter. When RCL is active or the receiver is not synchronized to the
QRSS pattern, then QPD maintains an output high.
RRING
TRING
TTIP
RTIP
VCO/PLL
21 of 32
NLOOP
RCL/QPD
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
20
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