ds2761 Maxim Integrated Products, Inc., ds2761 Datasheet - Page 20

• Manufacturer Part Number: ds2761
• Description: Ds2761 High-precision Li+ Battery Monitor
• Manufacturer: Maxim Integrated Products, Inc.

I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2761 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write
1, and read data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2761 is shown in Figure 17.
A presence pulse following a reset pulse indicates that the DS2761 is ready to accept a net address
command. The bus master transmits (Tx) a reset pulse for t
goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After
detecting the rising edge on the DQ pin, the DS2761 waits for t
for t
Figure 17. 1-WIRE INITIALIZATION SEQUENCE
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be t
DS2761 samples the 1-Wire bus line between 15
sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see Figure 18). For the bus
master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15
slot, the bus line must be pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a
logic-low level. The bus master must keep the bus line low for at least 1
DS2761 to present valid data. The bus master can then sample the data t
read-time slot. By the end of the read-time slot, the DS2761 releases the bus line and allows it to be
pulled high by the external pullup resistor. All read-time slots must be t
with a 1
PDL
SLOT
DQ
.
m
s minimum recovery time, t
(60
m
s to 120
LINE TYPE LEGEND:
m
s) in duration with a 1
t
m
RSTL
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2761 ACTIVE LOW
s after the start of the write time slot. For the host to generate a write 0 time
t
PDH
REC
, between cycles. See Figure 18 for more information.
m
20 of 24
m
s minimum recovery time, t
s and 60
t
PDL
RSTL
m
s after the line falls. If the line is high when
DS2761 ACTIVE LOW
RESISTOR PULLUP
. The bus master then releases the line and
PDH
t
RSTH
and then transmits the presence pulse
m
SLOT
s and then release it to allow the
RDV
(60
(15
REC
m
m
s to 120
s) from the start of the
, between cycles. The
m
s) in duration
PACK+
PACK-