cy2278a Cypress Semiconductor Corporation., cy2278a Datasheet
cy2278a
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cy2278a Summary of contents
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... The CY2278A is a Clock Synthesizer/Driver chip for Pentium, or Pentium II portable PCs designed with the 82430TX or sim- ilar core-logic chipsets. There are four options available as shown in the selector guide. The CY2278A outputs seven CPU clocks, three of which run at 3.3V and four run at either 2.5V or 3.3V, depending on the Logic Block Diagram X ...
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... CPUCLK0 PCICLK4 12 37 CPUCLK1 13 PCICLK5 36 V DDQ3 CPUCLK2 DDQ3 PCICLK6 15 34 SEL0 PCICLK7 17 32 SEL1 PCICLK8 DDQ3 SEL2 PCICLK9 20 29 CPU_RUN CLK8MHz 21 28 USB_RUN DDQ3 PCI_RUN USBCLK IRCLK CY2278A ...
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... Control input, stops all CPU clocks except XCPUCLK_F when driven LOW Power down input, shuts down device when driven LOW 2.5V or 3.3V CPU clock outputs 2.5V or 3.3V CPU clock output, free-running on CY2278A-1L only. This output is not free-running on the -2L, -3L, -4L configurations. 3.3V CPU clock output PCI clock outputs, free-running on CY2278A-1L, -3L, -4L only. This output is ...
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... Static Discharge Voltage ........................................... >2000V +0.5 DD (per MIL-STD-883, Method 3015, like V Description Test Conditions [6] Except Crystal Inputs [6] Except Crystal Inputs , V = 2.375V DDCPU DDQ2 , V = 2.375V DDCPU DDQ2 4 CY2278A (MHz) PPM 0 –1057 –1057 –1107 –1057 0 –171 –196 167 167 pins tied together) DD Min. Max. Unit 3.135 3 ...
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... 3.465V Loaded Outputs, DDQ3 IN DD CPU clocks = 66.67 MHz V = 3.465V Unloaded Outputs DDQ3 IN DD Current draw in power-down state 5 CY2278A Min. Max. Unit XCPUCLK 2 CPUCLK PCICLK USBCLK CLK8MHZ OH I ...
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... Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks (-3L configuration) Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks [10] Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI clock stabilization from power-up = 2.5V, CPUCLK duty cycle is measured at 1.25V. DDCPU 6 CY2278A Min. Typ. Max. Unit 0.6 4.0 V/ns 0.8 4.0 V/ns 0 ...
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... Switching Waveforms Duty Cycle Timing t OUTPUT All Outputs Rise/Fall Time OUTPUT XCPU-CPU Clock Skew XCPUCLK–CPUCLK t 5 XCPU-PCI Clock Skew XCPUCLK PCICLK CY2278A ...
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... CPUCLK on and CPUCLK off latency external CPUCLK cycles. 12. CPU_RUN may be applied asynchronously synchronized internally. 13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 14. PCI_RUN may be applied asynchronously synchronized internally. 15. USBCLK on and USBCLK off latency is 2 USBCLK cycles. 8 CY2278A ...
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... If a Ferrite Bead is used F– tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. is the loaded characteristic impedance trace from the clock generator V island. Ensure that the Ferrite Bead offers CY2278A of LOAD is the series terminating series ...
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... Document #: 38–00619–D V DDQ3 0 0 0.1 F OUTPUTS C LOAD Package Name Package Type Z48 48-Pin TSSOP Z48 48-Pin TSSOP Z48 48-Pin TSSOP Z48 48-Pin TSSOP 10 CY2278A V DDQ2 V DDCPU Operating Range Commercial Commercial Commercial Commercial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2278A 51-85059-A ...