cy28352oi-400t SpectraLinear Inc, cy28352oi-400t Datasheet - Page 4

• Manufacturer Part Number: cy28352oi-400t
• Description: Differential Clock Buffer/driver Ddr400 And Ddr333-compliant
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 28, 2006
Absolute Maximum Conditions
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum Power Supply: ................................................ 3.5V
DC Electrical Specifications
AC Electrical Specifications
V
V
V
V
V
I
V
V
V
V
I
I
I
I
C
fCLK
tDC
tlock
D
Tr / Tf
tpZL, tpZH
tpLZ, tpHZ
Notes:
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other.
IN
OZ
DDQ
DSTAT
DD
Parameter
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see Figure 7.
6. The value of V
7. All outputs switching loaded with 16 pF in 60Ω environment. SeeFigure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down
DD,
IL
IH
IL
IH
OL
OH
OUT
OC
IN
TYC
Parameter
spread of –0.5%.
A
VDD
Supply Voltage
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
Output Crossing
Voltage
High-Impedance Output
Current
Dynamic Supply
Current
Static Supply Current
PLL Supply Current
Input Pin Capacitance
OC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Duty Cycle
Output Clocks Slew Rate
Output Enable Time
(all outputs)
Output Disable Time
(all outputs)
Description
[6]
[7]
SS
DD
:...............................V
or AV
Description
DD
[5]
[4]
[7, 9]
: ............... V
[10]
Operating
SDATA, SCLK
SDATA, SCLK
V
FBIN
V
V
V
All V
A
[10]
CLKIN, FBIN
CLKIN, FBIN
[3]
VDD
IN
DD
DD
O
= GND or V
= 0V or V
DD
= 2.375V, I
= 2.375V, I
only
, FO = 273 MHz
Condition
DD
SS
IN
+ 0.3V
– 0.3V
O
OL
OH
= V
= V
= 12 mA
= –12 mA
DD
A
60 MHz to 170 MHz
170 MHz to 273 MHz
20% to 80% of V
DD
VDD
, CLKIN,
, V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
the range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
DD
Condition
< (V
= 2.5V to 2.7V
(V
0.6V
IN
DD
Min.
0.15
–10
–10
2.5
2.2
1.7
1.1
OD
or V
–
–
–
–
–
–
/2) –
DD
OUT
) < V
SS
V
Typ.
IN
235
DD
DD
or V
–
–
–
–
–
–
–
–
–
–
–
9
4
and V
/2
.
Min.
DD
60
40
49
48
–
1
–
–
).
OUT
(V
CY28352-400
should be constrained to
V
DD
0.3V
Typ.
DD
50
Max.
/2) + 0.15
–
–
–
–
–
3
3
300
2.7
1.0
0.6
10
10
12
–
–
–
1
6
– 0.4
DD
Page 4 of 7
Max.
273
100
2.5
60
51
52
Unit
MHz
mA
mA
mA
Unit
V/ns
µA
µA
pF
V
V
μs
V
V
V
V
V
V
V
ns
ns
%
%
%