cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 3

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
Pin Description
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Pin No.
SRCT_0/
SRCC0/
PCI4/FCTSEL1
VSS_PCI
VDD_PCI
ITP_SEL/PCIF0
CLKREQ7#
VTT_PWRGD#/PD
VDD_48
48M/FSA
VSS_48
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
FSB/TEST_MODE
CLKREQ6#
LCD100MT
LCD100MC
VDD_SRC
SRCT_1/SATAT,
SRCC_1/SATAC
SRCT_2
SRCC_2
VDD_SRC
SRCT_3
SRCC_3
CLKREQ4#
SRCT_4
SRCC_4
VSS_SRC
SRCT_5
(continued)
Name
I/O, SE, 33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
I/O, SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
O, DIF True Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output
O, DIF Complementary Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O,DIF True 100-MHz differential serial reference clock output/Differential 96/100-MHz
O,DIF Complementary 100-MHz differential serial reference clock output/Differential
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
GND
GND
GND
Type
I/O
I
I
I
I
I
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on VTTPWRGD#/PD assertion).
on VTTPWRGD#/PD assertion).
1 = CPU2_ITP, 0 = SRC10
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
3.3V LVTTL input. This pin is a level sensitive strobe. it latches data on the FSA,
FSB, FSC, FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time
input for controlling power down.
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
output Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
96/100-MHz SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD#/PD assertion.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
Ground for outputs.
Ground for outputs.
PRELIMINARY
FCTS E L1 P in 43
0 DOT96T
1 27M_NSS
P in 44
DOT96C
27M_SS
Description
P in 47
96/100M_T 96/100M_C
SRCT0
P in 48
SRCC0
CY28549
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