cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 11

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
Byte 15 Control Register 15
Table 6. Crystal Recommendations
The CY28549 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28549 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
14.31818 MHz
Frequency
Bit
2
1
0
(Fund)
Figure 1. Crystal Capacitive Clarification
@Pup
1
0
1
Cut
AT
Loading Load Cap
Parallel
IO_VOUT2
IO_VOUT1
IO_VOUT0
Name
20 pF
PRELIMINARY
0.1 mW
(max.)
IO_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 0.82V (Default)
100 = 0.86V
101 = 0.90V
110 = 0.93V
111 = Reserved
Drive
Shunt Cap
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
(max.)
5 pF
CLe
Cs1
Total Capacitance (as seen by the crystal)
=
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
C i1
Description
Ce = 2 * CL – (Cs + Ci)
C lock C hip
1
XTAL
Tolerance
35 ppm
(max.)
Ci2
+
X2
1
C e2
Ce2 + Cs2 + Ci2
Stability
30 ppm
(max.)
Cs2
1
CY28549
3 to 6p
Page 11 of 23
33 pF
Pin
Trim
2.8 pF
Trace
(max.)
Aging
5 ppm
)