cy28src01 Cypress Semiconductor Corporation., cy28src01 Datasheet - Page 2

• Manufacturer Part Number: cy28src01
• Description: Pci-express Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-00058 Rev. *A
Pin Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Pin No.
2, 5,16
3,4
1,6
14
15
12
13
10
11
7
9
8
SRC[T/C]0
VDD_SRC
VSS_SRC
VDD_REF
VSS_REF
SDATA
XOUT
VDDA
SCLK
VSSA
Name
IREF
XIN
I/O, PU SMBus compatible SDATA.This pin has an internal pull-up, but is tri-stated in
O, DIF Differential Selectable Serial reference clock.
PWR 3.3V power supply for SRC outputs
PWR 3.3V power supply for PLL
PWR Power for Xtal
GND
GND
GND
Type
I,PU
O
I
I
A precision resistor (475Ω) attached to this pin is connected to the internal current
reference.
SMBus compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in
powerdown.
powerdown.
Intel Type-X buffer.
Includes overclock support through SMBUS
14.318-MHz Crystal Input
14.318-MHz Crystal Output
Ground for SRC outputs
Analog Ground
Ground for Xtal
PRELIMINARY
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Description
CY28SRC01
Page 2 of 10
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