cy28src04 Cypress Semiconductor Corporation., cy28src04 Datasheet
cy28src04
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cy28src04 Summary of contents
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... PCI-Express Clock Generator • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 24-pin TSSOP package VDD_SRC SRCT[2:1],SRCC[2:1] • 3901 North First Street • San Jose CY28SRC04 Pin Configuration , CA 95134 • 408-943-2600 Revised June 20, 2005 ...
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... The slave receiver address is 11010010 (D2h). Description Bit 1 8 18: 27:21 28 CY28SRC04 Description Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeat start Slave address – 7 bits ...
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... SRC[T/C]3 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi- Enable SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable- only for CY28SRC01 0 = Disable (Hi-Z Enable Reserved CY28SRC04 Block Read Protocol Description Acknowledge from slave Byte Count from slave – ...
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... Reserved Reserved Reserved Reserved SRC Spread Spectrum Enable 0 = Spread off Spread on Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28SRC04 Description Description Description Description Description Page ...
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... Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Drive Load Cap (max.) 12 pF– CY28SRC04 Description Description Description Description Shunt Cap Tolerance Stability (max.) (max.) (max ±50 ppm ± ...
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... Crystal Recommendations The CY28SRC04 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28SRC04 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... PD asserted, Outputs driven PD asserted, Outputs Hi-Z Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3V 0.7V DD CY28SRC04 Min. Max. –0.5 4.6 –0.5 4.6 –0 0.5 DD –65 ...
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... OH Determined as a fraction of 2*(T – T )/( Math averages Figure 3 Math averages Figure 3 See Figure 3. Measure SE Measurement at 1.5V Measurement at 1.5V@1us : : : : : : Figure 3. 0.7V Load Configuration CY28SRC04 Condition Min 9.997001 10.00300 ns OX 9.997001 10.05327 ns OX 10.12800 9.872001 ns OX 9.872001 10.17827 ns OX – – OX – ...
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... PRELIMINARY Package Type PIN 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 24 0.25[0.010] 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. BSC GAUGE PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY28SRC04 Product Flow Commercial 70qC Commercial 70qC 0°-8° 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85119-*A Page ...
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... Document History Page Document Title: CY28SRC04 PCI-Express Clock Generator Document Number: 001-00043 REV. ECN NO. Issue Date ** 371761 See ECN *A 384078 See ECN Document #: 001-00043 Rev. *A PRELIMINARY Orig. of Change RGL New Data Sheet RGL 1) Swap Pin 1 and 2 in Pin Configuration 2) Swap Pin 5 and 6 in Pin Configuration ...