cy241v08a-13 Cypress Semiconductor Corporation., cy241v08a-13 Datasheet

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... Application compatibility for a wide variety of designs Output Frequencies One copy of 27 MHz One copy of 74.175824 MHz OUTPUT DIVIDER 74.175824MHz XBUF/27MHz VSS • 3901 North First Street • San Jose CY241V08A-13 VCXO Control Curve linear , CA 95134 • 408-943-2600 Revised June 02, 2004 [+] Feedback ...

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... Reference crystal input. VDD 2 Voltage supply. VCXO 3 Input analog control for VCXO. VSS 4 Ground. XBUF/27 MHz 5 27 MHz buffered crystal output. 74.175824 MHz 6 74.175824 MHz clock output Connect. XOUT 8 Reference crystal output. Document #: 38-07675 Rev. ** CY241V08A-13 Description Page [+] Feedback ...

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... Duty Cycle is defined in Figure 1, 50 Output Clock Edge Rate, Measured from 20 pF. See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD CY241V08A-13 Min. Typ. Max. Unit – 27 – MHz – 14 – pF Ω – ...

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... DUT GND Figure 1. Duty Cycle Definition 80 20 /t3 (0 Package Type Operating Range Commercial CY241V08A-13 Min. Typ. Max. Unit – 190 – ps – 250 – ps – 1860 – ps – 280 – ps – ...

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... S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.016[0.406] 0.0098[0.249] 0.035[0.889] CY241V08A-13 MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Page [+] Feedback ...

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... Document History Page Document Title: CY241V08A-13 Clock Generator with VCXO Document Number: 38-07675 REV. ECN NO. Issue Date ** 230995 See ECN Document #: 38-07675 Rev. ** Orig. of Change Description of Change RGL New Data Sheet CY241V08A-13 Page [+] Feedback ...