cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 10

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Serial Programming Interface (SPI) Protocol
and Timing
The CY27EE16ZE utilizes a 2-serial-wire interface SDAT and
SCLK that operates up to 400 kbits/sec in Read or Write mode.
The basic Write serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is
illustrated in Figure 4.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is LOW as illustrated in Figure 5.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 6.
Start Sequence – Start Frame is indicated by SDAT going
LOW when SCLK is HIGH. Every time a start signal is given,
the next 8-bit data must be the device address (7 bits) and a
R/W bit, followed by register address (8 bits) and register data
(8 bits).
Stop Sequence – Stop Frame is indicated by SDAT going
HIGH when SCLK is HIGH. A Stop Frame frees the bus for
writing to another part on the same bus or writing to another
random register address.
Acknowledge Pulse
During Write Mode the CY27EE16ZE will respond with an
Acknowledge pulse after every 8 bits. This is accomplished by
pulling the SDAT line LOW during the N*9
illustrated in Figure 7. (N = the number of bytes transmitted).
During Read Mode the acknowledge pulse after the data
packet is sent is generated by the master.
Device Addressing
The first four bits of the device address word for the eight
EEPROM scratchpad blocks are 1000. The 5th, 6th, and 7th
bits are the address bits (A2, A1, A0 respectively) for the slices
of 2K EEPROM. The first seven bits of the device address
word for the clock configuration EEPROM block are 1101000.
The first seven bits of the device address word for the clock
configuration SRAM block are 1101001. The final bit of the
address specifies the operation (HIGH/1 = Read, LOW/0 =
Write)
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit word address after
the device address word, which is followed by an acknowl-
edgment bit from the EEPROM (ack = 0/LOW). The next 8 bits
must contain the data word intended for storage. After the data
word is received, the EEPROM responds with another
th
clock cycle as
acknowledge bit (ack = 0/LOW), and the device that is
addressing the EEPROM must end the write sequence with a
stop condition. The EEPROM now enters an internal write
process transferring the data received to nonvolatile memory.
During, and until completion of, this internal write process, the
EEPROM will not respond to other commands.
Writing Multiple Bytes
The CY27EE16ZE is capable of receiving up to 16 consec-
utive written bytes. In order to write more than one byte at a
time, the device addressing the EEPROM does not end the
write sequence with a stop condition. Instead, the device can
send up to fifteen more bytes of data to be stored. After each
byte, the EEPROM responds with an acknowledge bit, just like
after the first byte. The EEPROM will accept data until the
acknowledge bit is responded to by the stop condition, at
which time it enters the internal write process as described in
the section above. When receiving multiple bytes, the
CY27EE16ZE internally increments the address of the last 4
bits in the address word. After 16 bytes are written, that incre-
menting brings it back to the first word that was written. If more
than 16 bytes are written, the CY27EE16ZE will overwrite the
first bytes written.
Read Operations
Read operations are initiated the same way as Write opera-
tions except that the R/W bit of the slave address is set to ‘1’
(HIGH). There are three basic read operations: current
address read, random read, and sequential read.
Current Address Read
The CY27EE16ZE has an onboard address counter that
retains 1 more than the address of the last word access. If the
last word written or read was word ‘n,’ then a current address
read operation would return the value stored in location ‘n+1’.
When the CY27EE16ZE receives the slave address with the
R/W bit set to a ‘1,’ the CY27EE16ZE issues an acknowledge
and transmits the 8-bit word. The master device does not
acknowledge the transfer, but does generate a STOP
condition, which causes the CY27EE16ZE to stop trans-
mission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first
the word address must be set. This is accomplished by
sending the address to the CY27EE16ZE as part of a write
operation. After the word address is sent, the master
generates a START condition following the acknowledge. This
terminates the write operation before any data is stored in the
address, but not before the internal address pointer is set.
Next the master reissues the control byte with the R/W byte
set to ‘1.’ The CY27EE16ZE then issues an acknowledge and
transmits the 8-bit word. The master device does not
acknowledge the transfer, but does generate a STOP
condition which causes the CY27EE16ZE to stop trans-
mission.
CY27EE16ZE
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