cy2dl818 Cypress Semiconductor Corporation., cy2dl818 Datasheet - Page 2

• Manufacturer Part Number: cy2dl818
• Description: 1 8 Clock Fanout Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07058 Rev. *B
Pin Description
Output Drive Control for Standard and Bus/B/Hi-Drive
Input Receiver Configuration for Differential or LVTTL/LVCMOS
Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
Power Supply Characteristics
1, 9,12,
18,19,20,38
2,3,4,5,8, 13
14,15,16,17,29
10,11
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
6
7
Parameter
Ground
Ground
Pin Number
I
CCD
VCC
VCC
I
C
Pin 7 Binary Value
Pin 6 Binary Value
InCONFIG
CNTRL
Dynamic Power Supply Current V
Total Power Supply Current
Input Condition
0
1
1
0
G
V
Input A, Input B(#)
Q1A, Q1B, Q2A, Q2B,
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B, Q6A, Q6B,
Q7A, Q7B, Q8A, Q8B
InConfig
CNTRL
Input B (–) Pin 11
Input B (–) Pin 11
Input A (+) Pin 10
Input A (+) Pin 10
Input A (+) Pin 10
Input A (+) Pin 10
Input B (–) Pin 11
Input B (–) Pin 11
DD
ND
Description
Pin Name
LVTTL in LVCMOS
LVDS
LVPECL
Input Receiver Family
Hi-drive/Bus/B
Drive STD
Standard
POWER
POWER
Default: LVPECL / LDVS
Optional: LVTTL/LVCMOS
single pin.
LDVS
LVTTL / LVCMOS
LVTTL / LVCMOS
Input toggling 50% Duty Cycle, Outputs Open
V
Input toggling 50% Duty Cycle, Outputs Open
fL = 100 MHz
Pin Standard Interface
LVTTL/LVCMOS INPUT LOGIC
DD
DD
= Max
= Max
Input Logic
Input – Bar
Input – Bar
Input – Bar
Input – Bar
Input
Input
Input
Input
Single-ended non-inverting, inverting, void of bias resistors.
Low-voltage differential signaling
Low-voltage pseudo (positive) emitter coupled logic
Test Conditions
Impedance
Ground
Power Supply
Differential input pair or single line.
LVPECL/LVDS default. See InConfig below.
Differential Outputs
Converts inputs from the default
See Figure 5 and Figure 6 for additional information
Converts into a high-speed driver.
Logic = 0 = 100 ohm
Logic = 1 = 50-ohm “default pull-up”
See Figure 7 for additional Information
100 Ohms
100 Ohms
To
50 Ohms
50 Ohms
LVTTL/LVCMOS
LVPECL/LVDS
Input Receiver Type
Output Logic Q Pins, Q1A or Q1
Pin Description
Input – Bar
Input – Bar
Input – Bar
Input – Bar
Min.
(logic = 1) “default pull-up”
Input
Input
Input
Input
Output Voltage Value
(logic = 0)
V
V = 1/2 * V
V = 2 * V
Typ. Max.
0.40
O =
40
V = V
Voutput
CY2DL818
O
0.5
80
O
O
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mA/MHz
Unit
mA
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