cy2xf23 Cypress Semiconductor Corporation., cy2xf23 Datasheet - Page 3

• Manufacturer Part Number: cy2xf23
• Description: High Performance Lvds Oscillator With Frequency Margining - I 2c Control
• Manufacturer: Cypress Semiconductor Corporation.

Programming Variables
Output Frequencies
The CY2XF23 is programmed with up to four independent output
frequencies, which are then selected using the I
device can synthesize frequencies to a resolution of 1 part per
million (ppm), but the actual accuracy of the output frequency is
limited by the accuracy of the integrated reference crystal.
The CY2XF23 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF23 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
Table 2. Device Programming Variables
Memory Map
Five fields can be written via the I
define the output frequency. As shown in
words is a 6-byte field. When writing to a frequency word, all 6
bytes should be written. They may be written either as individual
byte writes, or as a block write. The currently selected frequency
word should not be written to. All four words are symmetrical,
meaning that a 6-byte value that is valid for one word is also valid
for any of the other words, and produces the same frequency.
The fifth field is the select byte, located at byte address 40h. The
value written into the two least significant bits determines the
active frequency word. The other bits of the byte are reserved
and should be written with the values indicated in the table.
Users should never write to any address other than the 25 bytes
described here.
Document Number: 001-53145 Rev. *A
Output Frequency 0
Output Frequency 1
Output Frequency 2
Output Frequency 3
Optimization (phase noise or jitter)
Temperature range (Commercial or Industrial)
Variable
2
C Bus. Four frequency words
Table
2
3, each of these
C interface. The
PRELIMINARY
Table 3. Frequency Words
Table 4. Register 40h: Select Byte
Serial Interface Protocol and Timing
The CY2XF23 uses pins SDA and SCLK for an I
operates up to 100 kbits/sec in Read or Write mode. The
CY2XF23 is always a slave on this bus, meaning that it never
initiates a bus transaction. The basic Write protocol is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; and so on, until STOP Bit. The basic serial format
is illustrated in
Device Address
The device address is a 7-bit value. The default serial interface
address is 69H.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is LOW as illustrated in
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in
START Sequence - Start Frame is indicated by SDA going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
STOP Sequence - Stop Frame is indicated by SDA going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write Mode, the CY2XF23 responds with an
Acknowledge (ACK) pulse after every eight bits. This is accom-
plished by pulling the SDA line LOW during the N*9
as illustrated in
transmitted). After the data packet is sent during Read Mode, the
master generates the acknowledge.
Frequency
Bits
7:2
1:0
Word
0
1
2
3
000000
00
(binary)
Default
Value
Figure 4
Figure 6
Figure 7
Byte Addresses
1Ch to 21h
16h to 1Bh
10h to 15h
22h to 27h
Reserved
Word Select Selects the Frequency
on page 5.
(hex)
on page 5.
on page 6. (N = the number of bytes
Name
Reserved. Always write
this value.
Word to determine the
output frequency. 00
selects Word 0; 01 selects
Word 1; 10 selects Word 2;
11 selects Word 3.
(Select Byte 40h)
Description
Word Select
Figure 5
CY2XF23
00
01
10
11
th
Page 3 of 11
2
C Bus that
clock cycle
on page 5.
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