cy2v995 Cypress Semiconductor Corporation., cy2v995 Datasheet - Page 3

• Manufacturer Part Number: cy2v995
• Description: 2.5/3.3v 200-mhz Multi-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07435 Rev. *A
Table 2. Power-down Mode
In addition to the feedback dividers, the CY2V995 includes
output dividers on Bank3 and Bank4, which are controlled by
3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively.
Table 3. Output Divider Settings – Bank 3
Table 4. Output Divider Settings – Bank 4
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 5.
Table 5. Output Frequency Settings
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V995 PLL operating frequency range that
corresponds to each FS level is given in Table 6.
Notes:
1Qn or 2Qn
3Qn
4Qn
5.
6.
7.
8.
Configuration
Connected to
FB Input
LL disables outputs if TEST = MID and sOE# = HIGH.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH or MID, sOE# disables them LOW when PE = LOW.
These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (F
a given reference frequency (F
a VCO frequency that is within the range specified by FS pin. Please see Table 6.
V
and V
DD
3F[1:0]
4F[1:0]
Q1/3/4 must not be set at a level higher than that of V
Other
Other
PD#
LL
LL
DD
HH
HH
H
L
[5]
[5]
Q4 = 2.5V.
N x F
N x K x F
N x M x F
1Q[0:1] and
2Q[0:1]
REF
M – Bank4 Output Divider
K – Bank3 Output Divider
REF
[7]
REF
REF
Output Frequency
) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate
N /x (1 / K) x
F
N x F
N x (M / K) x
F
REF
REF
Power Down
3Q[0:1]
Inverted
CY2V995
Enabled
REF
2
4
1
2
1
[6]
N x (1 / M) x
F
N x (K / M) x
F
N x F
REF
REF
DD
4Q[0:1]
. They can be set at different levels from each other, e.g. V
REF
Table 6. Frequency Range Select
The PE pin determines Whether the outputs synchronize to
the rising or the falling edge of the reference signal, as
indicated in Table 7.
Table 7. PE Settings
The CY2V995 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (V
than that on any one of the output power supplies.
Table 8. Power Supply Constraints
Governing Agencies
The following agencies provide specifications that apply to the
CY2V995. The agency name and relevant specification is
listed below.
3.3V
2.5V
V
DD
Agency Name
FS
UL-194_V0
M
H
L
JEDEC
PE
IEEE
H
L
MIL
3.3V or 2.5V
DD
V
DD
) must be set a level which is equal or higher
2.5V
Q1
[8]
DD
PLL Frequency Range
3.3V or 2.5V
= 3.3V, V
V
48 to 100 MHz
96 to 200 MHz
DD
JESD 65 (Skew, Jitter)
94 (Moisture Grading)
24 to 50 MHz
2.5V
883E Method 1012.1
JESD 51 (Theta JA)
1596.3 (Jiter Specs)
Synchronization
(Therma Theta JC)
Q3
Specification
DD
[8]
Negative
Positive
Q1 = 3.3V, V
CY2V995
3.3V or 2.5V
Page 3 of 10
V
DD
2.5V
DD
Q4
Q3 = 2.5V
NOM
[8]
) at
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