74VHC374MTCX Fairchild Semiconductor, 74VHC374MTCX Datasheet - Page 2

IC FLIP FLOP OCT D 3ST 20TSSOP

74VHC374MTCX

Manufacturer Part Number
74VHC374MTCX
Description
IC FLIP FLOP OCT D 3ST 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VHCr
Type
D-Type Busr
Datasheet

Specifications of 74VHC374MTCX

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
185MHz
Delay Time - Propagation
5.4ns
Trigger Type
Positive Edge
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
VHC
Technology
CMOS
Number Of Bits
8
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
2.5/3.3/5V
Package Type
TSSOP
Propagation Delay Time
16.5ns
Low Level Output Current
8mA
High Level Output Current
-8mA
Frequency (max)
75MHz
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74VHC374MTCX
Manufacturer:
OMRON
Quantity:
29 462
Part Number:
74VHC374MTCX
Manufacturer:
FAIRCHILD
Quantity:
3 600
©1992 Fairchild Semiconductor Corporation
74VHC374 Rev. 1.3
Logic Symbol
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
= LOW-to-HIGH Transition
D
H
X
L
n
Inputs
CP
X
IEEE/IEC
OE
H
L
L
Outputs
O
H
L
Z
n
Figure 1.
2
Functional Description
The VHC374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
www.fairchildsemi.com

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