MX29LV004CB Macronix, MX29LV004CB Datasheet

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MX29LV004CB

Manufacturer Part Number
MX29LV004CB
Description
4M-Bit CMOS Single Voltage 3V Only Flash Memory
Manufacturer
Macronix
Datasheet
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8
• Single power supply operation
• Fully compatible with MX29LV004T/B device
• Fast access time: 55R/70/90ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
• Status Reply
GENERAL DESCRIPTION
The MX29LV004C T/B is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits. MXIC's Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The MX29LV004C
T/B is packaged in 40-pin TSOP and 32-pin PLCC. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.
The standard MX29LV004C T/B offers access time as
fast as 55ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV004C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV004C T/B uses a command register to manage
this functionality. The command register allows for 100%
P/N:PM1148
- 3.0V only operation for read, erase and program
operation
- 30mA maximum active current
- 0.2uA typical standby current
- Byte Programming (9us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
- Data# Polling & Toggle bit for detection of program
1
MX29LV004C T/B
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
• Ready/Busy# pin (RY/BY#)
• Sector protection
• CFI (Common Flash Interface) compliant
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
• Package type:
• Compatibility with JEDEC standard
• 20 years data retention
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV004C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
and erase operation completion.
- Provides a hardware method of detecting program or
erase operation completion.
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
- Flash device parameters stored on the device and
provide the host system to access
- T = Top Boot Sector
- B = Bottom Boot Sector
- 40-pin TSOP
- 32-pin PLCC
- All Pb-free devices are RoHS Compliant
- Pinout and software compatible with single-power
supply Flash
3V ONLY FLASH MEMORY
REV. 1.1, AUG. 30, 2005

Related parts for MX29LV004CB

MX29LV004CB Summary of contents

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FEATURES • Extended single - supply voltage range 2.7V to 3.6V • 524,288 x 8 • Single power supply operation - 3.0V only operation for read, erase and program operation • Fully compatible with MX29LV004T/B device • Fast access time: ...

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PIN CONFIGURATIONS 40 TSOP (Standard Type) (10mm x 20mm) A16 1 A15 2 A14 3 A13 4 A12 5 A11 WE# 9 RESET RY/BY# 12 A18 ...

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... SA2 64Kbytes SA3 64Kbytes SA4 64Kbytes SA5 64Kbytes SA6 64Kbytes SA7 32Kbytes SA8 8Kbytes SA9 8Kbytes SA10 16Kbytes Table 2: MX29LV004CB SECTOR ARCHITECTURE Sector Sector Size Byte Mode SA0 16Kbytes SA1 8Kbytes SA2 8Kbytes SA3 32Kbytes SA4 64Kbytes SA5 64Kbytes SA6 64Kbytes ...

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BLOCK DIAGRAM CONTROL CE# OE# INPUT WE# LOGIC RESET# (for 40-TSOP) ADDRESS LATCH A0-A18 AND BUFFER Q0-Q7 P/N:PM1148 MX29LV004C T/B PROGRAM/ERASE HIGH VOLTAGE STATE REGISTER FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV DATA LATCH PROGRAM ...

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AUTOMATIC PROGRAMMING The MX29LV004C T/B is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming ...

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Table 1 and Table 2). The rest of address bits, as shown in table3, are don't care. Once all neces- sary bits have been set as required, the ...

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TABLE 4. MX29LV004C T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID 4 555H AAH 2AAH Sector Protect 4 555H AAH 2AAH Verify Program 4 555H AAH 2AAH Chip ...

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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the TABLE 5. MX29LV004C ...

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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...

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... Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of B5H for MX29LV004CT, B6H for MX29LV004CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two " ...

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... A0 A1 Manufacture code VIL VIL Device code VIH VIL for MX29LV004CT Device code VIH VIL for MX29LV004CB Sector Protection X VIH Verification X VIH READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm ...

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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...

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ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector ...

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Only erase operations can convert a "0" "1". WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 10 and ...

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The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the ...

Page 16

If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and ...

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WE# pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...

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Table 8. CAPACITANCE SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance Table 9. DC CHARACTERISTICS TA = -40 Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ILO Output Leakage Current ...

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AC CHARACTERISTICS TA = -40 Table 10. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay tDF OE# High to Output Float (Note1) tOEH ...

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Figure 1. SWITCHING TEST CIRCUITS DEVICE UNDER TEST Figure 2. SWITCHING TEST WAVEFORMS 3.0V 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are ...

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Figure 3. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1148 MX29LV004C T/B tRC ADD Valid tACC tCE tOE tOEH tACC DATA Valid 22 tDF ...

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AC CHARACTERISTICS TA = -40 Table 11. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL Read ...

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AC CHARACTERISTICS TA = -40 Table 12. Alternate CE# Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...

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Figure 4. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1148 MX29LV004C T/B ADD Valid tAH tWPH tWP tCWC tCH tDS tDH DIN 25 ...

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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming completion can be verified by ...

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Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1148 MX29LV004C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES ...

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Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# tCP CE# tWS tDS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. ...

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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by Data# Polling and toggle bit checking after ...

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Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1148 MX29LV004C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...

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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A17 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by Data# Polling and toggle bit ...

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Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1148 MX29LV004C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector ...

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Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 10ms time delay must be put into consideration. P/N:PM1148 MX29LV004C T/B START ...

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Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Protect or Sector Unprotect Data 60h 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0. ...

Page 35

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM1148 MX29LV004C T/B START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector ...

Page 36

Figure 15. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control 12V 3V A9 tVLHT 12V 3V OE# tVLHT WE# CE# Data A18-A12 P/N:PM1148 MX29LV004C T/B tWPP 1 tOESP Sector Address 36 Verify tVLHT 01H F0H tOE REV. 1.1, AUG. ...

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Figure 16. SECTOR PROTECTION ALGORITHM (A9, OE# Control) No PLSCNT=32? Yes Device Failed P/N:PM1148 MX29LV004C T/B START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read ...

Page 38

Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM1148 MX29LV004C T/B START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? ...

Page 39

Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) A1 12V 3V A9 tVLHT A6 12V 3V OE# tVLHT WE# CE# Data A18-A12 Notes: tWPP1 (Write pulse width for sector protect)=100ns min, 10us(typ.). tWPP2 (Write pulse width for sector ...

Page 40

Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE# Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1148 MX29LV004C T/B START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# ...

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WRITE OPERATION STATUS Figure 20. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming P/N:PM1148 MX29LV004C T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ...

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Figure 21. TOGGLE BIT ALGORITHM NO Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1148 MX29LV004C T/B Start Read Q7-Q0 Read Q7-Q0 ...

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Figure 22. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, ...

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Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC VA Address tACC tCE CE# tCH tOE OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after ...

Page 45

Table 13. AC CHARACTERISTICS (for 40-pin TSOP package type) Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP ...

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Table 14. TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 25. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM 12V RESET Vcc ...

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Figure 27. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM1148 MX29LV004C T/B Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V ...

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Figure 28. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q7 ...

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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...

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Table 15. ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured 3V. 3.Maximum values ...

Page 51

QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29LV004CT/ CB) MX29LV004CT/CB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and ...

Page 52

TABLE 18-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description N Device size (2 bytes) Flash device interface code (refer to the CFI publication 100) Maximum number of bytes in multi-byte write (not ...

Page 53

... MX29LV004CTTI-70 70 MX29LV004CBTI-70 70 MX29LV004CTTI-90 90 MX29LV004CBTI-90 90 MX29LV004CTQC-55R 55 MX29LV004CBQC-55R 55 MX29LV004CTQC-70 70 MX29LV004CBQC-70 70 MX29LV004CTQC-90 70 MX29LV004CBQC-90 70 MX29LV004CTQI-55R 55 MX29LV004CBQI-55R 55 MX29LV004CTQI-70 70 MX29LV004CBQI-70 70 MX29LV004CTQI-90 70 MX29LV004CBQI-90 70 MX29LV004CTTC-55Q 55 MX29LV004CBTC-55Q 55 MX29LV004CTTC-70G 70 MX29LV004CBTC-70G 70 MX29LV004CTTC-90G 90 MX29LV004CBTC-90G 90 MX29LV004CTTI-55Q 55 MX29LV004CBTI-55Q 55 MX29LV004CTTI-70G 70 MX29LV004CBTI-70G 70 MX29LV004CTTI-90G 90 MX29LV004CBTI-90G 90 P/N:PM1148 MX29LV004C T/B Operating Current Standby Current MAX. (mA) MAX. (uA ...

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... PART NO. Access Time (ns) MX29LV004CTQC-55Q 55 MX29LV004CBQC-55Q 55 MX29LV004CTQC-70G 70 MX29LV004CBQC-70G 70 MX29LV004CTQC-90G 90 MX29LV004CBQC-90G 90 MX29LV004CTQI-55Q 55 MX29LV004CBQI-55Q 55 MX29LV004CTQI-70G 70 MX29LV004CBQI-70G 70 MX29LV004CTQI-90G 90 MX29LV004CBQI-90G 90 P/N:PM1148 MX29LV004C T/B Operating Current Standby Current MAX. (mA) MAX. (uA PACKAGE Remark 32 Pin PLCC PB free ...

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PART NAME DESCRIPTION 004 P/N:PM1148 MX29LV004C T OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package SPEED: 55: 55ns 70: 70ns 90: 90ns TEMPERATURE RANGE: ...

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PACKAGE INFORMATION P/N:PM1148 MX29LV004C T/B 56 REV. 1.1, AUG. 30, 2005 ...

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P/N:PM1148 MX29LV004C T/B 57 REV. 1.1, AUG. 30, 2005 ...

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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Added "Recommended Operating Conditions" 1.1 1. Modified "Low power consumption--active current" from 20mA(Max 30mA(Max.) 2. Added description about Pb-free devices are RoHS Compliant P/N:PM1148 MX29LV004C T/B Page P1 ...

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... MX29LV004C T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...

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