MX29F200CT Macronix International, MX29F200CT Datasheet - Page 11

• Manufacturer Part Number: MX29F200CT
• Description: 2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
• Manufacturer: Macronix International

ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions. Another Erase Suspend command can be
written after the chip has resumed erasing. However, a
time delay must be required after the erase resume
command, if the system implements an endless erase
suspend/resume loop, or the number of erase suspend/
resume is exceeded 1024 times. The erase times will be
expended if the erase behavior always be suspended.
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.
Once the Automatic Program command is initiated, the
next WE# pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising edge
of the WE# pulse. The rising edge of WE# also begins
the programming operation. The system does not require
to provide further controls or timings. The device will
automatically provide an adequate internally generated
program pulse and verify margin.
If the program operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
DATA# POLLING-Q7
The MX29F200C T/B also features Data# Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.
While the Automatic Programming algorithm is in opera-
tion, an attempt to read the device will produce the
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complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
written to Q7. The Data# Polling feature is valid after the
rising edge of the fourth WE# pulse of the four write pulse
sequences for automatic program.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data# Polling feature is valid after the rising
edge of the sixth WE# pulse of six write pulse sequences
for automatic chip/sector erase.
The Data# Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
RY/BY#:Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algo-
rithm is in progress or complete. The RY/BY# status is
valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain
output, several RY/BY# pins can be tied together in
parallel with a pull-up resistor to Vcc.
If the outputs is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence(prior to the program or erase opera-
tion), and during the sector time-out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6 to
toggle. The system may use either OE# or CE# to control
the read cycles. When the operation is complete, Q6
stops toggling.
MX29F200C T/B
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REV. 1.0 , DEC. 14, 2005