MBM29PL12LM Fujitsu Media Devices, MBM29PL12LM Datasheet - Page 35

• Manufacturer Part Number: MBM29PL12LM
• Description: FLASH MEMORY 128 M (16M x 8/8M x 16) BIT
• Manufacturer: Fujitsu Media Devices

DQ
Data Polling
DQ
Toggle Bit I
The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce
reverse data last written to DQ
device will produce true data last written to DQ
of fourth write pulse in the four write pulse sequence. During the Embedded Erase Algorithm, an attempt to read
the device will produce a “0” at the DQ
to read device will produce a “1” at the DQ
Algorithm” in ■FLOW CHART.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write cycles. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors.
Otherwise, the status may become invalid.
If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 µs, then
the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing
are protected, Data Polling on DQ
not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ
samples the DQ
Algorithm operation and DQ
on DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend mode or sector erase time-out.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the Data
Polling timing specifications and diagram.
The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write cycles. For
chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write
cycles. The Toggle Bit I is active during the sector time out.
In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 µs and
then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for
the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 400 µs and
then drop back into read mode, having data kept remained.
Either CE or OE toggling will cause the DQ
Algorithm Operations” in ■TIMING DIAGRAM for the Toggle Bit I timing specifications and diagram.
7
6
7
to DQ
0
will be read on the successive read attempts.
7
output, it may read the sequence flag or valid data. Even if the device completes the Embedded
7
at one instant of time, and then that byte’s valid data the next. Depending on when the system
6
will stop toggling and valid data will be read on the next successive attempts. During
7
has a valid data, the data outputs on DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt to read the
6
7
toggling between 1 and 0. Once the Embedded Program or Erase Algorithm
is active for approximately 400 µs, then the device returns to read mode. If
7
output. Upon completion of the Embedded Erase Algorithm, an attempt
7
output. The flowchart for Data Polling (DQ
6
7
to toggle. See “Toggle Bit l Timing Diagram during Embedded
. For programming, the Data Polling is valid after the rising edge
6
to DQ
MBM29PL12LM
0
may still be invalid. The valid data
7
) is shown in “Data Polling
7
) may change
10
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