MBM29LV160T Fujitsu Media Devices, MBM29LV160T Datasheet - Page 25

• Manufacturer Part Number: MBM29LV160T
• Description: 16M (2M x 8/1M x 16) BIT
• Manufacturer: Fujitsu Media Devices

RESET
Hardware Reset Pin
Word/Byte Configuration
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-up Write Inhibit
Handling of SON Package
The MBM29LV160T/B device may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode t
device requires an additional t
the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 12 for the timing diagram.
Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160T/B device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
DQ
the lowest address bit and DQ
operation and hence commands are written at DQ
13 and 14 for the timing diagrams.
The MBM29LV160T/B is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.
15
CC
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ
CC
Write Inhibit
MBM29LV160T
level is greater than V
READY
after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
LKO
RH
CC
8
to DQ
. It is the users responsibility to ensure that the control pins are logically correct
before it allows read access. When the RESET pin is low, the device will be in
< V
LKO
14
IL
, the command register is disabled and all internal program/erase circuits
CC
) for at least 500 ns in order to properly reset the internal state machine.
bits are tri-stated. However, the command bus cycle is always an 8-bit
-80/-90/-12
is above 2.3 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
IL
, CE = V
0
to DQ
IH
7
will not accept commands on the rising edge of WE.
/MBM29LV160B
IH
and DQ
, or WE = V
8
to DQ
IH
. To initiate a write, CE and WE must
IL
15
. The RESET pin has a pulse
bits are ignored. Refer to Figures
15
-80/-90/-12
/A
-1
CC
pin becomes
power-up
CC
less
0
to
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