FS6011-02 AMI, FS6011-02 Datasheet - Page 4

• Manufacturer Part Number: FS6011-02
• Description: DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC
• Manufacturer: AMI

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D[2]
4.1
The ACLK frequency is controlled by register bits D[0],
D[1], and D[2] accessed via the serial interface. The
ACLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
Table 3: ACLK Frequency Select
NOTE: Contact AMI for custom PLL frequencies
4.2
The ACLK frequencies shown may be smoothly modified
to a slightly higher or lower value under register control.
Register bit D[3] must be a logic-one to activate this
mode. The value of D[4] controls whether the frequency
will be adjusted slightly low (D[4] = 0) or high (D[4] = 1).
Table 4: Audio Off Speed Frequencies
D[4]
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D[1]
D[3]
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Audio PLL Clock Frequencies (ACLK)
Audio Clock Off-Speed Frequencies
D[0]
0
1
0
1
0
1
0
1
D[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PLL DIVIDER
1024 / 2250
1024 / 3375
1024 / 4500
1024 / 6750
1568 / 3750
1568 / 2500
1568 / 7500
1024 / 1125
D[1]
RATIO
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OVERSAMPLING
44.1kHz x 256 / 2
48kHz x 256 / 2
32kHz x 256 / 2
44.1kHz x 256
44.1kHz x 384
PLL DIVIDER
48kHz x 256
32kHz x 256
48kHz x 512
1023 / 2250
1023 / 3375
1023 / 4500
1023 / 6750
1567 / 3750
1567 / 2500
1567 / 7500
1023 / 1125
1025 / 2250
1025 / 3375
1025 / 4500
1025 / 6750
1569 / 3750
1569 / 2500
1569 / 7500
1025 / 1125
AUDIO
RATIO
11.2824
16.9236
24.5520
12.3000
11.2968
16.9432
24.6000
11.2896
16.9344
12.276
5.6412
8.2000
6.1500
4.1000
5.6484
ACLK
(MHz)
12.288
5.6448
24.576
8.184
6.138
4.092
ACLK
(MHz)
8.192
6.144
4.096
4
4.3
The UCLK frequency is controlled by register bits D[5],
D[6] and D[7], accessed via the serial interface. UCLK
frequencies listed below are derived via the PLL Divider
Ratio from a reference frequency of 27MHz.
Table 5: UCLK Frequency Select
NOTE: Contact AMI for custom PLL frequencies
4.4
The PCLK frequency is controlled by the logic levels on
the PSEL0 and PSEL1 inputs. These inputs have weak
pull-downs. PCLK frequencies listed below are derived
via the PLL Divider Ratio from a reference frequency of
27MHz.
Table 6: PCLK Frequency Select
NOTE: Contact AMI for custom PLL frequencies
D[7]
PSEL1
0
0
0
0
1
1
1
1
0
0
1
1
D[6]
Utility PLL Clock Frequencies (UCLK)
Processor PLL Frequencies (PCLK)
0
0
1
1
0
0
1
1
PSEL0
0
1
0
1
D[5]
0
1
0
1
0
1
0
1
PLL DIVIDER RATIO
PLL DIVIDER RATIO
1568 / 3750
1024 / 1125
544 / 375
728 / 375
16 / 27
35 / 33
32 / 27
40 / 27
50 / 27
60 / 41
10 / 9
1
UCLK (MHz)
PCLK (MHz)
16.0000
28.6363
11.2896
27.0000
39.1680
52.4160
30.0000
24.5760
32.0000
40.0000
50.0000
39.5122
July 1998
7.20.98