SC18IS601 Philips Semiconductors, SC18IS601 Datasheet
SC18IS601
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SC18IS601 Summary of contents
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... I the host to communicate directly with other I operate controls all the I The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source: internal (SC18IS600) versus external (SC18IS601). 2. Features I SPI slave interface ...
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NXP Semiconductors 4. Block diagram SC18IS600 CONTROL RESET LOGIC MISO MOSI SPI SCLK CS INT INTERRUPT CONTROL LOGIC OSCILLATOR ON-CHIP RC OSCILLATOR Fig 1. Block diagram of SC18IS600 SC18IS600_601_3 Product data sheet BUFFER CONTROLLER GENERAL PURPOSE Rev. 03 — 13 ...
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... NXP Semiconductors SC18IS601 CONTROL RESET MISO MOSI SCLK CS INT INTERRUPT CONTROL external clock input OSCILLATOR (CLKIN) Fig 2. Block diagram of SC18IS601 SC18IS600_601_3 Product data sheet LOGIC SPI LOGIC Rev. 03 — 13 December 2006 SC18IS600/601 SPI C-BUS BUFFER CONTROLLER GENERAL PURPOSE I/Os 002aab784 © ...
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... SCLK MOSI 10 GPIO2 SDA 9 GPIO1 SCL Fig 4. SC18IS601 pin configuration for TSSOP16 Type Description I/O programmable I/O pin I Chip select. When CS is LOW, the SC18IS600/601 is selected. I Master Reset. When active (LOW), RESET sets internal registers to the default values, and resets the I Table 3 ...
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... Functional description The SC18IS600/601 acts as a bridge between a SPI interface and an I SPI master device to communicate with I Mode 3 of the SPI specification and can operate Mbit/s (SC18IS601). 6.1 Internal registers The SC18IS600/601 provides internal registers for monitoring and control. These registers are shown in paragraphs ...
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NXP Semiconductors 6.2.1.1 Quasi-bidirectional output configuration Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the pin. This is possible because when the pin outputs a logic HIGH weakly driven, allowing ...
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NXP Semiconductors 6.2.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the pin when the pin latch contains a logic used as a logic output, a pin ...
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NXP Semiconductors Fig 8. Push-pull output configuration 6.2.2 I/O pins state register (IOState) When read, this register returns the actual state of all programmable and quasi-bidirectional I/O pins. When written, each register bit will be transferred to the corresponding I/O ...
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... The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1 will enable the time-out function. On the SC18IS600 the time-out oscillator operates at 57.6 kHz. For the SC18IS601 the time-out oscillator frequency can be determined using the following formula: Time-out oscillator frequency This oscillator is fed into a 16-bit down counter. The down counter’s lower nine bits are loaded with ‘ ...
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NXP Semiconductors 2 6.2.6 I C-bus status register (I2CStat) This register reports the results of I SC18IS600/601 and Table 8. I C-bus status Register Bit 7 Bit 6 Bit 5 value 0xF0 0xF1 1 ...
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... NXP Semiconductors 6.3 External clock input (SC18IS601) In this device, the processor clock is derived from an external source driving the CLKIN pin. The clock rate may be from MHz. 2 6.4 I C-bus serial interface 2 I C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • ...
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NXP Semiconductors Fig 11. SPI single master multiple slaves configuration 6.6 SPI message format 6.6.1 Write N bytes to I SPI host sends 0x00 NUMBER SLAVE ADDRESS COMMAND OF BYTES CS SCLK MOSI command 0x00 2 Fig 12. Write N ...
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NXP Semiconductors 6.6.2 Read N bytes from I Fig 13. Read N bytes from I Once the host issues this command, the SC18IS600/601 will start an I transaction on the I SC18IS600/601 will place this data in the receiver buffer, ...
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NXP Semiconductors When the host issues a Read Buffer command, the SC18IS600/601 will return the data in the read buffer on the MISO pin. Note that the Read Buffer will be overwritten if an additional ‘Read N bytes’ ...
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NXP Semiconductors 6.6.7 Write to SC18IS600/601 internal registers Fig 18. Write to SC18IS600/601 internal registers A Write Register function is initiated by sending a 0x20 command followed by an internal register address to be written (see address. Only one register ...
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NXP Semiconductors 6.6.9 Power-down mode Fig 20. Power-down mode The SC18IS600/601 can be placed in a low-power mode where the internal oscillator is stopped and it will no longer respond to SPI messages. Enter the Power-down mode by sending the ...
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NXP Semiconductors 8. Static characteristics Table 11. Static characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply ...
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... Table 12. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency (SC18IS600) External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time CLCX ...
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... Table 13. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency (SC18IS600) External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time CLCX ...
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NXP Semiconductors SS SPICLK (input) MISO (output) not defined MOSI (input) Fig 21. SPI slave timing (Mode 0.45 V Fig 22. External clock timing SC18IS600_601_3 Product data sheet t SPIF T CLCL t SPILEAD t ...
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NXP Semiconductors Table 14. Additional SPI AC characteristics Symbol Parameter t SPICLK HIGH time SPICLKW t CS HIGH time CSW t SPI enable lag time 1 SPILAG1 t delay time d SCLK t SPILEAD CS SDA 2 Fig 23. SPI ...
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NXP Semiconductors 10. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. ...
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NXP Semiconductors 11. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 11.1 Introduction to soldering Soldering ...
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NXP Semiconductors 11.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 12. Abbreviations Table 17. Acronym ASCII GPIO UART LSB MSB 2 I ...
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... Product data sheet Rev. 03 — 13 December 2006 SC18IS600/601 SPI to I Change notice Supersedes - SC18IS600_601_2 and Figure 2 “Block diagram of SC18IS601” 2 C-bus serial clock output” register”: modified: changed “register data” minimum value changed from “3 s” to SPICLKW - SC18IS600_601_1 ...
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NXP Semiconductors 14. Legal information 14.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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... C-bus address register (I2CAdr 6.2.4 I C-bus clock rates register (I2CClk 6.2.5 I C-bus time-out register (I2CTO 6.2.6 I C-bus status register (I2CStat 6.3 External clock input (SC18IS601 6.4 I C-bus serial interface . . . . . . . . . . . . . . . . . . 11 6.5 Serial Peripheral Interface (SPI 6.6 SPI message format . . . . . . . . . . . . . . . . . . . . 12 2 6.6.1 Write N bytes to I C-bus slave device ...