RM5231-150-Q PMC-Sierra Inc, RM5231-150-Q Datasheet - Page 25

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RM5231-150-Q

Manufacturer Part Number
RM5231-150-Q
Description
RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released
Manufacturer
PMC-Sierra Inc
Datasheet
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002165, Issue 1
3.32 Boot-Time Modes
Mode
bit
0
4:1
7:5
8
10:9
11
12
low frequency operation allows the initialization information to be kept in a low cost EPROM or a
system interface ASIC.
Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock run continuously from the
assertion of VccOK.
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream
Description
Reserved: Must be zero
Write-back data rate (W = write data transfer, x = wait
state)
Pclock to SysClock Multiplier
Mode Bits 7:5
Specifies byte ordering. Logically ORed with
BigEndian input signal.
Non-Block Write Protocol
Timer Interrupt Enable/Disable
Reserved: Must be zero
0: WWWWWWWW
1: WWxWWxWWxWWx
2: WWxxWWxxWWxxWWxx
3: WxWxWxWxWxWxWxWx
4: WWxxxWWxxxWWxxxWWxxx
5: WWxxxxWWxxxxWWxxxxWWxxxx
6: WxxWxxWxxWxxWxxWxxWxxWxx
7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx
8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx
9-15 reserved
0: Little endian
1: Big endian
00: R4000 compatible
01: reserved
10: pipelined
11: write re-issue
0: Enable the timer interrupt on Int5*
1: Disable the timer interrupt on Int5*
000
001
010
011
100
101
110
111
Multiply by 9
Multiply by 5
Multiply by 8
Multiply by 2
Multiply by 3
Multiply by 4
Multiply by 6
Multiply by 7
Mode Bit 20=0
Multiply by 4.5
Multiply by 2.5
Multiply by 3.5
Mode Bit 20=1
n/a
n/a
n/a
n/a
n/a
RM5231™ Microprocessor with 32-bit System Bus Data Sheet
Mode
bit
14:13
15
17:16
19:18
20
21
255:22 Reserved: Must be zero
Description
Output driver strength - 100% = fastest
Reserved: Must be zero
System configuration identifiers - software
visible in Config[21..20] register
Reserved: Must be zero
Select SysClock to PClock Multiply Mode
Reserved: Must be one
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
0: Integer Multipliers
1: Half-Integer Multipliers
Released
25

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