RM5231-150-Q PMC-Sierra Inc, RM5231-150-Q Datasheet - Page 22

• Manufacturer Part Number: RM5231-150-Q
• Description: RM5231 Microprocessor with 32-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002165, Issue 1
3.24 Handshake Signals
3.25 Non-overlapping System Interface
The RM5231 supports one- to four-byte transfers as well as block transfers on the SysAD bus. In
the case of a sub-word transfer, the two low-order address bits give the byte address of the transfer,
and the SysCmd bus indicates the number of bytes being transferred.
There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are
used by an external device to indicate to the RM5231 whether it can accept a new read or write
transaction. The RM5231 samples these signals before deasserting the address on read and write
requests.
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*. The RM5231 responds by asserting Release* to release the system interface to slave
state.
ValidOut* and ValidIn* are used by the RM5231 and the external device respectively to indicate
that there is a valid address, a command, or data on the SysAD and SysCmd buses. The RM5231
asserts ValidOut* when it is driving these buses with a valid address, a command or data, and the
external agent drives ValidIn* when it has control of the system interface and is driving a valid
address, a command or data.
The RM5231 requires a non-overlapping system interface. This means that only one processor
request may be outstanding at a time and that the request must be serviced by an external agent
before the RM5231 issues another request. The RM5231 can issue read and write requests to an
external device, whereas an external device can issue null and write requests to the RM5231.
For processor reads the RM5231 asserts ValidOut* and simultaneously drives the address and
read command on the SysAD and SysCmd buses respectively. If the system interface has RdRdy*
asserted, then the processor tristates its drivers and releases the system interface to the slave state
by asserting Release*. The external device can then begin sending data to the RM5231.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern is “WWWWWWWW”,
indicating that data can be transferred on every clock with no wait states in-between.
RM5231™ Microprocessor with 32-bit System Bus Data Sheet
Released
22