LTC4252-2 Linear Technology, LTC4252-2 Datasheet - Page 17

• Manufacturer Part Number: LTC4252-2
• Description: Negative Voltage Hot Swap Controllers
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
of 2.5% or more will eventually trip the circuit breaker and
shut down the LTC4252. Figure 5 shows the circuit breaker
response time in seconds normalized to 1µF for I
0µA. The asymmetric charging and discharging of C
fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8µA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 4V
threshold. TIMER starts with a 5.8µA pull-down until it
reaches the 1V threshold. Then, the 5.8µA pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8µA
pull-down cycles and three 5.8µA pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
t
C
SHUTDOWN
T
( )
t
µ
F
0.01
0.1
Figure 5. Circuit-Breaker Response Time
10
1
=
0
[
(
=
235 8 8
C
7 3
T
20
(µF)
t
•
U
.
5 8
FAULT DUTY CYCLE (%)
.
V C
+
=
µ
•
[(235.8 + 8 • I
40
A
•
U
I
T
4
DRN
60
)
4
DRN
•
D
I
) • D – 5.8]
W
DRN
−
80
4252-1/2 F05
5 8
= 0µA
.
]
100
U
DRN
T
is a
(4)
(5)
=
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A in
about 230µs. Connecting an external capacitor C
SS to ground modifies the ramp to approximate an RC
response of:
An internal resistive divider (95k/5k for the LTC4252 or
47.5k/2.5k for the LTC4252A) scales V
times to give the analog current limit threshold:
This allows the inrush current to be limited to V
The offset voltage, V
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
GATE
GATE is pulled low to V
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58µA current source charges the MOSFET gate and
any associated external capacitance. V
drive to no more than 14.5V.
Gate-drain capacitance (C
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
V
V
SS
ACL
LTC4252A-1/LTC4252A-2
( )
t
( )
t
≈
=
V
LTC4252-1/LTC4252-2
SS
V
SS
20
•
( )
⎛
⎜
⎜
⎝
t
1
−
OS
−
e
V
(10mV), ensures C
⎛
⎜
⎝
OS
−
R
EE
SS SS
GD
•
t
under any of the following
C
) feedthrough at the first
⎞
⎟
⎠
⎞
⎟
⎟
⎠
SS
IN
SS
(t) down by 20
limits the gate
is sufficiently
ACL
SS
17
(t)/R
425212fb
from
(6)
(7)
IN
S
.