LTC4252-2 Linear Technology, LTC4252-2 Datasheet - Page 12

• Manufacturer Part Number: LTC4252-2
• Description: Negative Voltage Hot Swap Controllers
• Manufacturer: Linear Technology

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OPERATIO
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4252 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or
power conversion circuitry with an external MOSFET switch
(see Figure 1). Both inrush control and short-circuit pro-
tection are provided by the MOSFET.
A detailed schematic for the LTC4252A is shown in Fig-
ure 2. – 48V and – 48RTN receive power through the
longest connector pins and are the first to connect when
the board is inserted. The GATE pin holds the MOSFET off
during this time. UV and OV determine whether or not the
MOSFET should be turned on based upon internal high
accuracy thresholds and an external divider. UV and OV do
double duty by also monitoring whether or not the connec-
tor is seated. The top of the divider detects – 48RTN by way
of a short connector pin that is the last to mate during the
insertion sequence.
12
BACKPLANE
–48RTN
–48V
LONG
LONG
Figure 1. Basic LTC4252 Hot Swap Topology
PLUG-IN BOARD
U
LTC4252
+
C
LOAD
+
–
CONVERTER
ISOLATED
MODULE
DC/DC
–
+
LOW
VOLTAGE
CIRCUITRY
4252-1/2 F01
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage V
2. The voltage at UV > V
3. The voltage at OV < V
4. The (SENSE – V
5. The voltage at SS is < 0.2V (20 • V
6. The voltage on the TIMER capacitor (C
7. The voltage at GATE is < 0.5V (V
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8µA
into C
stops and TIMER discharges C
until the aforementioned conditions are once again met. If
C
SS and GATE pins are released. GATE sources 58µA
(I
tance. The SS voltage ramp limits V
inrush current. PWRGD pulls active low when GATE is
within 2.8V of V
–48RTN
T
GATE
–48V
successfully charges to 4V, TIMER pulls low and both
SHORT
T
), charging the MOSFET gate and associated capaci-
LONG
LONG
. If V
Figure 2. –48V, 2.5A Hot Swap Controller
IN
30.1k
390k
1%
1%
R1
R2
, UV or OV falls out of range, the start-up cycle
IN
and DRAIN is lower than V
EE
C1
10nF
) voltage is < 50mV (V
IN
UVHI
OVLO
exceeds V
C
1µF
IN
68nF
C
0.68µF
.
C
.
T
3 × 1.8k IN SERIES
SS
T
to less than 1V, then waits
1/4W EACH
LKO
OV
UV
TIMER
SS
V
GATEL
EE
SENSE
OS
0.02Ω
10nF
C
LTC4252A-1
R
R
(UVLO).
C
T
S
IN
).
SENSE
) is < 1V (V
).
V
IN
to control the
CB
10Ω
R
DRAIN
C
DRNL
IRF530S
).
GATE
Q1
C
100µF
LOAD
.
TMRL
425212fb
4252-1/2 F02
R
1M
D
+
).