LTC4099 Linear Technology Corporation, LTC4099 Datasheet - Page 27
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LTC4099
Manufacturer Part Number
LTC4099
Description
I2C Controlled USB Power Manager/Charger
Manufacturer
Linear Technology Corporation
Datasheet
1.LTC4099.pdf
(36 pages)
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APPLICATIONS INFORMATION
nonlinear characteristic of capacitance versus voltage.
The actual in-circuit capacitance of a ceramic capacitor
should be measured with a small AC signal and DC bias,
as is expected in-circuit. Many vendors specify the ca-
pacitance versus voltage with a 1V
as a result, overstate the capacitance that the capacitor
will present in the application. Using similar operating
conditions as the application, the user must measure
or request from the vendor the actual capacitance to
determine if the selected capacitor meets the minimum
capacitance that the application requires.
Overprogramming the Battery Charger
The USB high power specifi cation allows for up to 2.5W
to be drawn from the USB port. The LTC4099’s switching
regulator regulates the voltage at V
above the voltage at BAT while limiting power to less
than the amount programmed at CLPROG. The charger
should be programmed, with the PROG pin, to deliver
the maximum safe charging current without regard to
the USB specifi cations. If there is insuffi cient current
available to charge the battery at the programmed rate,
the charger will reduce charge current until the system
load on V
satisfi ed. Programming the charger for more current
than is available will not cause the average input cur-
rent limit to be violated. It will merely allow the battery
charger to make use of all available power to charge the
battery as quickly as possible, and with minimal power
dissipation within the charger.
OUT
is satisfi ed and the V
RMS
BUS
OUT
V1
V2
AC test signal and,
current limit is
D2
to a level just
Figure 5. Dual Overvoltage Protection
R1
D1
M1
M2
Overvoltage Protection
It is possible to protect both V
overvoltage damage with several additional components
as shown in Figure 5. Schottky diodes D1 and D2 pass
the larger of V1 and V2 to R1 and OVSENS. If either
V1 or V2 exceeds 6V plus the Schottky forward voltage,
OVGATE will be pulled to GND and both the WALL and
USB inputs will be protected. Each input is protected up
to the drain-source breakdown, BV
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.2k resistor must be
sized appropriately to dissipate the resultant power.
For example, a 1/8W 6.2k resistor can have at most
√1/8W
With the 6V at OVSENS, the maximum overvoltage
magnitude that this resistor can withstand is 34V. A
1/4W 6.2k resistor raises this value to 45V. OVSENS’s
absolute maximum current rating of 10mA imposes an
upper limit of 68V protection.
Table 10. Recommended NMOS FETs for the Overvoltage
Protection Circuit
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin as it may adversely affect operation.
NTLJS4114
IRLML2502
Si2302ADS
NMOS FET
FDN3725
C1
WALL
OVGATE
V
GND
OVSENS
6.2k = 28V applied across its terminals.
LTC4099
BUS
4099 F05
BV
30V
20V
30V
20V
DSS
50mΩ
70mΩ
40mΩ
35mΩ
R
ON
BUS
DSS
and WALL from
, of M1 and M2.
LTC4099
2mm 2mm DFN
PACKAGE
SOT-23
SOT-23
SOT-23
27
4099f