LTC4099 Linear Technology Corporation, LTC4099 Datasheet - Page 22

• Manufacturer Part Number: LTC4099
• Description: I2C Controlled USB Power Manager/Charger
• Manufacturer: Linear Technology Corporation

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LTC4099
OPERATION
SDA line (HIGH) during the acknowledge clock cycle.
The LTC4099 pulls down the SDA line during the write
acknowledge clock pulse so that it is a stable LOW
during the HIGH period of this clock pulse.
When the LTC4099 is read from, it releases the SDA line
so that the master may acknowledge receipt of the data.
Since the LTC4099 only transmits one byte of data, a master
not acknowledging the data sent by the LTC4099 has no
specifi c consequence on the operation of the I
However, without a read acknowledge from the master, a
pending interrupt from the LTC4099 will not be cleared
and the IRQ pin will not be released.
Slave Address
The LTC4099 responds to a 7-bit address which has been
factory programmed to 0b0001001[R/W]. The LSB of
the address byte, known as the read/write bit, should be
0 when writing data to the LTC4099, and 1 when reading
data from it. Considering the address an 8-bit word, then
the write address is 0x12, and the read address is 0x13.
The LTC4099 will acknowledge both its read and write
addresses.
Sub-Addressed Writing
The LTC4099 has three command registers for control
input. They are accessed by the I
addressed writing system.
Each write cycle of the LTC4099 consists of exactly three
bytes. The fi rst byte is always the LTC4099’s write address.
The second byte represents the LTC4099’s sub address.
The sub address is a pointer which directs the subsequent
data byte within the LTC4099. The third bye consists of
the data to be written to the location pointed to by the
sub address. The LTC4099 contains control registers at
only three sub address locations: 0x00, 0x01 and 0x02.
Only the two LSBs of the sub address byte are decoded,
the remaining bits are don’t-cares. Therefore, a write to
sub address 0x06 for example, is effectively a write to
sub address 0x02.
22
2
C port via a sub-
2
C port.
Bus Write Operation
The master initiates communication with the LTC4099
with a START condition and the LTC4099’s write address.
If the address matches that of the LTC4099, the LTC4099
returns an acknowledge. The master should then deliver
the sub address. Again, the LTC4099 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of
its acknowledge by the LTC4099. This procedure must be
repeated for each sub address that requires new data. After
one or more cycles of [ADDRESS][SUB-ADDRESS][DATA],
the master may terminate the communication with a STOP
condition. Alternatively, a repeat START condition can be
initiated by the master and another chip on the I
be addressed. This cycle can continue indefi nitely, and the
LTC4099 will remember the last input of valid data that it
received. Once all chips on the bus have been addressed
and sent valid data, a global STOP can be sent and the
LTC4099 will update its command latches with the data
that it had received.
Bus Read Operation
The bus master reads the status of the LTC4099 with a
START condition followed by the LTC4099 read address. If
the read address matches that of the LTC4099, the LTC4099
returns an acknowledge. Following the acknowledgement
of its read address, the LTC4099 returns one bit of status
information for each of the next eight clock cycles. A STOP
command is not required for the bus read operation.
Input Data
Table 1 illustrates the three data bytes that may be writ-
ten to the LTC4099. The fi rst byte at sub address 0x00
controls the three input current limit bits I
three battery charge current control bits I
and the two C/x state-of-charge indication control bits
COVERX1 and COVERX0.
The input current limit settings are decoded according to
Table 2. This table indicates the maximum current that will
be drawn from the V
V
available. Any additional power will be drawn from the bat-
tery. The default state for the input current limit setting is
000, representing the low power 100mA USB setting.
OUT
(battery charger plus system load) exceeds the power
BUS
pin in the event that the load at
CHARGE2
LIM2
2
-I
-I
C bus can
LIM0
CHARGE0
, the
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