LTC3834 Linear Technology, LTC3834 Datasheet - Page 12

• Manufacturer Part Number: LTC3834
• Description: Synchronous Step-Down Controller
• Manufacturer: Linear Technology

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OPERATION
LTC3834
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3834’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an exter-
nal clock source, the PLLLPF pin can be fl oated, tied to
INTVCC, or tied to SGND to select 400kHz, 530kHz or
250kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3834
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the PLLLPF
pin and SGND to serve as the PLL’s loop fi lter. The LTC3834
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external top MOSFET to the rising
edge of the synchronizing signal.
The typical capture range of the LTC3834’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee to be between 140kHz and 650kHz. In other
words, the LTC3834’s PLL is guaranteed to lock to an
external clock source whose frequency is between 140kHz
and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3834 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3834 in PolyPhase applications. The clock output
12
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal, as summarized in Table 1.
The phases are calculated relative to the zero degrees
phase being defi ned as the rising edge of the top gate
driver output (TG).
The CLKOUT pin has an open-drain output device. Normally,
a 10k to 100k resistor can be connected from this pin to a
voltage supply that is less than or equal to 8.5V.
Table 1
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V
than 10% higher than its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open-drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the V
±10% of the 0.8V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the V
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 8.5V.
FB
pin voltage is within the ±10% requirement, the
V
Floating
INTV
PHASMD
GND
CC
FB
pin voltage is not within
FB
CLKOUT PHASE
pin rises to more
120°
180°
90°
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