LTC3411 Linear Technology, LTC3411 Datasheet - Page 3

• Manufacturer Part Number: LTC3411
• Description: 1.25A/ 4MHz/ Synchronous Step-Down DC/DC Converter
• Manufacturer: Linear Technology

ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
SYMBOL
PGOOD
R
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3411E is guaranteed to meet specified performance from
0 C to 70 C. Specifications over the – 40 C to 85 C operating ambient
termperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3411 is tested in a feedback loop which servos V
midpoint for the error amplifier (V
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
PI FU CTIO S
SHDN/R
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing this
pin to SV
down all functions are disabled.
SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op-
eration of the device. When tied to SV
Mode operation or pulse skipping mode is selected, re-
spectively. If this pin is held at half of SV
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to this
pin. When synchronized to an external clock pulse skip
mode is selected.
SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout Consider-
ations).
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV
PGOOD
U
T
IN
(Pin 1): Combination Shutdown and Timing
U
causes the device to be shut down. In shut-
PARAMETER
Power Good Threshold
Power Good Pull-Down On-Resistance
U
IN
ITH
to PGND.
= 0.6V).
IN
or SGND, Burst
IN
, the forced
A
= 25 C. V
FB
CONDITIONS
V
V
FB
FB
The
to the
Ramping Up, SHDN/R
Ramping Down, SHDN/R
IN
denotes the specifications which apply over the full operating
= 3.3V, R
Note 5: T
according to the following formula:
Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125 C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
PGND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of C
PV
to PGND.
SV
powered from this pin. Must be closely decoupled to
SGND. SV
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within 7.5% of regulation.
V
external resistive divider across the output. Nominal volt-
age for this pin is 0.8V.
I
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
TH
FB
LTC3411EDD: T
LTC3411EMS: T
IN
IN
(Pin 10): Error Amplifier Compensation Point. The
T
(Pin 9): Receives the feedback voltage from the
(Pin 6): Main Supply Pin. Must be closely decoupled
(Pin 7): The Signal Power Pin. All active circuitry is
= 324k unless otherwise specified. (Note 2)
J
is calculated from the ambient T
T
= 1V
IN
T
= 1V
must be greater than or equal to PV
J
J
= T
= T
OUT
A
A
+ (P
+ (P
, and (–) terminal of C
D
D
• 43 C/W)
• 120 C/W)
MIN
A
and power dissipation P
– 7.6
TYP
118
6.8
LTC3411
IN
MAX
200
.
sn3411 3411fs
IN
.
UNITS
D
3
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