LTC3411 Linear Technology, LTC3411 Datasheet - Page 13

• Manufacturer Part Number: LTC3411
• Description: 1.25A/ 4MHz/ Synchronous Step-Down DC/DC Converter
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V
bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta or single inductor, positive buck/
boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>1uF) input
capacitors. The discharged input capacitors are effectively
put in parallel with C
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A hot swap controller is
designed specifically for this purpose and usually incorpo-
rates current limiting, short-circuit protection, and soft-
starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3411 circuits: 1) LTC3411 V
2) switching losses, 3) I
%Efficiency = 100% – (L1 + L2 + L3 + ...)
IN
drops toward V
U
OUT
, causing a rapid drop in V
2
R losses, 4) other losses.
U
OUT
W
, the load step capa-
IN
U
current,
OUT
. No
1) The V
electrical characteristics which excludes MOSFET driver
and control currents. V
loss that increases with V
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from V
ground. The resulting dQ/dt is a current out of V
typically much larger than the DC bias current. In continu-
ous mode, I
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
and thus their effects will be more pronounced at higher
supply voltages.
3) I
internal switches, R
continuous mode, the average output current flowing
through inductor L but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
follows:
The R
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
R
I
2
2
R Losses are calculated from the DC resistances of the
SW
R losses = I
DS(ON)
= (R
IN
current is the DC supply current given in the
GATECHG
DS(ON)
for both the top and bottom MOSFETs can be
OUT
TOP)(DC) + (R
2(R
DS(ON)
= f
SW
IN
O
SW
, and external inductor, RL. In
current results in a small (<0.1%)
(QT + QB), where QT and QB are
2
R losses:
IN
+ RL)
and the duty cycle (DC) as
, even at no load.
DS(ON)
LTC3411
BOT)(1 – DC)
IN
has adequate
sn3411 3411fs
IN
13
that is
IN
to
IN