LTC2752 Linear Technology, LTC2752 Datasheet - Page 19

• Manufacturer Part Number: LTC2752
• Description: Dual16-Bit SoftSpan IOUT DACs
• Manufacturer: Linear Technology

The offset adjust pin V
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
A 5V control voltage applied to V
–512 LSB in any output range, assuming a 5V reference
voltage at R
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
The gain error adjust pins GE
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V
delta is inverted and attenuated by a factor of 128.
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
operaTion
∆V
∆V
∆V
∆V
∆V
∆GE
OS
OS
OS
REFX
OS
=
= –(
= –(
= –(
[
LSB
V
= –(
GEADJX
V
INX
1
1
1
RINX
/
/
/
]
128
64
32
1
.
=
/
)V
)V
128
–
)V
OSADJX
OSADJX
V
• 512
)GE
OSADJX
V
VOSADJX
RINX
OSADJX
ADJX
REFX
can be used to null unipolar
• 512
. In voltage terms, the V
[0V to 5V, ±2.5V spans]
[0V to 10V, ±5V, –2.5V to
7.5V spans]
[±10V span]
ADJX
OSADJX
can be used to null
produces ∆V
REFX
OS
=
The V
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling perfor-
mance of the LTC2752. They should be shorted to GND
if not used.
The GE
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2752, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply V
approximately 2V; and stays asserted until any valid Update
command is executed.
OSADJX
ADJX
pins have an input impedance of 2.56MΩ, and
pins have an input impedance of 1.28MΩ.
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LTC2752
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2752f