LTC2752 Linear Technology, LTC2752 Datasheet - Page 13

• Manufacturer Part Number: LTC2752
• Description: Dual16-Bit SoftSpan IOUT DACs
• Manufacturer: Linear Technology

operaTion
Output Ranges
The LTC2752 is a dual, current-output, serial-input precision
multiplying DAC with selectable output ranges. Ranges
can either be programmed in software for maximum flex-
ibility—each of the DACs can be programmed to any one
of six output ranges—or hardwired through pin-strapping.
Two unipolar ranges are available (0V to 5V and 0V to 10V),
and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to
7.5V). These ranges are obtained when an external pre-
cision 5V reference is used. The output ranges for other
reference voltages are easy to calculate by observing that
each range is a multiple of the external reference voltage.
The ranges can then be expressed: 0 to 1×, 0 to 2×, ±0.5×,
±1×, ±2×, and –0.5× to 1.5×.
Manual Span Configuration
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2752 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to V
then set via hardware pin strapping of pins S2, S1 and S0
(rather than through the SPI port); and Write and Update
commands have no effect on the active output span. See
Figure 1 and Table 3.
Figure 1. Using M-SPAN to Configure the LTC2752
for Single-Span Operation (±10V Range Shown)
LTC2752
M-SPAN
S2
S1
S0
CS/LD SDI
DD
V
V
. The active output range for all DACs is
DD
DD
SCK
DAC A
DAC B
2752 F01
–
+
–
+
±10V
±10V
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
Input and DAC Registers
The LTC2752 has 5 internal registers for each DAC, a total
of 10 registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers—one set for the
code data, and one for the output range of the DAC—plus
one readback register. Double buffering provides the ca-
pability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Note that updates always include both Code and Span
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been changed via a Write operation.
Serial Interface
When the CS/LD pin is taken low, the data on the SDI
pin is loaded into the shift register on the rising edge of
the clock (SCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2752 is a 4-bit command
word (C3 C2 C1 C0), followed by a 4-bit address word
(A3 A2 A1 A0) and 16 data (span or code) bits, MSB first.
Figure 2 shows the SDI input word syntax to use when
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