LTC2492 Linear Technology, LTC2492 Datasheet - Page 26

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC2492
The input data is shifted through the SDI pin on the rising
edge of SCK (including the fi rst rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 32nd rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is fl oating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2492’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when CS
is pulsed HIGH-LOW-HIGH in order to test the conversion
status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. If CS goes HIGH before the time t
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2492 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
26
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Digital Signal Levels
The LTC2492’s digital interface is easy to use. Its digital
inputs SDI, F
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as
100μs.
The digital input signal range is 0.5V to V
transitions, the CMOS input circuits draw dynamic current.
For optimal performance, application of signals to the
serial data interface should be reserved for the sleep and
data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital
interface and the external oscillator pin (F
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
diffi cult when shared control lines are used and multiple
refl ections occur.
Parallel termination near the input pin of the LTC2492 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depending
on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, F
no degradation occurs. On the other hand, if an external
oscillator is used (F
the conversion cycle. Moreover, the digital fi lter rejection
is minimal at the clock rate applied to F
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
O
) remain static during the conversion cycle and
O
, CS, and SCK (in external serial clock mode)
O
driven externally) it is active during
CC
O
O
. Care must be
) may degrade
– 0.5V. During
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