LTC2492 Linear Technology, LTC2492 Datasheet - Page 24

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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(INTERNAL)
APPLICATIONS INFORMATION
LTC2492
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 32nd
falling edge of SCK (see Figure 10). On the rising edge of
CS, the device aborts the data output state and immediately
initiates a new conversion. In order to program a new input
channel, 8 SCK clock pulses are required. If the data output
sequence is aborted prior to the 8th falling edge of SCK,
the new input data is ignored and the previously selected
input channel remains valid. If the rising edge of CS occurs
after the 8th falling edge of SCK, the new input channel is
loaded and valid for the next conversion cycle. If CS goes
high between the 8th falling edge and the 16th falling edge
of SCK, the new channel is still loaded, but the converter
confi guration remains unchanged. In order to program
both the input channel and converter confi guration, CS
must go high after the 16th falling edge of SCK (at this
point all data has been shifted into the device).
24
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
<t
EOCTEST
BIT 31
1
EOC
1
BIT 30
“0”
0
Figure 9. Internal Serial Clock, Single Cycle Operation
2
0.1μF
10μF
2.7V TO 5.5V
BIT 29
SIG
EN
3
0.1V TO V
REFERENCE
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
MSB
ANALOG
SGL
INPUTS
VOLTAGE
4
CC
ODD
5
12
13
14
10
11
8
9
7
A2
V
REF
REF
CH0
CH1
CH2
CH3
COM
6
CC
LTC2492
+
–
A1
7
SDO
GND
SCK
SDI
DATA INPUT/OUTPUT
CS
F
O
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after V
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is fl oating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has fi nished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
A0
5
6
8
2
3
1
4
EN2
9
4-WIRE
SPI INTERFACE
IM
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10
FA
11
V
BIT 20 BIT 19
CC
FB
12
OPTIONAL
10k
SPD
13
BIT 18 BIT 17
CC
14
exceeds 2V. An internal
DON'T CARE
BIT 0
32
Hi-Z
CONVERSION
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