LTC2262-14 Linear Dimensions Semiconductor, LTC2262-14 Datasheet - Page 19

• Manufacturer Part Number: LTC2262-14
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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APPLICATIONS INFORMATION
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
so the rising edge of CLKOUT
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT
setup-and-hold time when latching the data, the CLKOUT
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2262-14 can also phase shift the CLKOUT
CLKOUT
trol register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
Another control register bit can invert the polarity of
CLKOUT
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overfl ow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4
D0-D13, OF
CLKOUT
ENC
+
+
+
–
and CLKOUT
signals by serially programming mode con-
Figure 14. Phase Shifting CLKOUT
–
, independently of the phase shift.
226214 F14
+
PHASE
SHIFT
can be used to latch the
135°
180°
225°
270°
315°
45°
90°
0°
CLKINV
+
. To allow adequate
0
0
0
0
1
1
1
1
MODE CONTROL BITS
CLKPHASE1
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
+
+
+
,
/
Table 1. Output Codes vs Input Voltage
A
(2V Range)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is “randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is ap-
plied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
that is centered around midscale, the digital outputs toggle
between mostly 1s and mostly 0s. This simultaneous
IN
+
– A
IN
–
OF
1
0
0
0
0
0
0
0
0
1
(OFFSET BINARY)
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
D13-D0
LTC2262-14
(2’s COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D13-D0
19
226214p