LTC2262-12 Linear Dimensions Semiconductor, LTC2262-12 Datasheet
LTC2262-12
Related parts for LTC2262-12
LTC2262-12 Summary of contents
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... CLOCK Ultralow Power 1.8V ADC DESCRIPTION The LTC designed for digitizing high frequency, wide dynamic range signals. The LTC2262-12 is perfect for demanding commu- nications applications with AC performance that includes 70.5dB SNR and 88dB spurious free dynamic range (SFDR Ultralow jitter of 0.17ps ...
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... LTC2262-12 ABSOLUTE MAXIMUM RATINGS Supply Voltages ( ....................... –0. Analog Input Voltage ( PAR/SER, SENSE) (Note 3) ...........–0. www.datasheet4u.com + Digital Input Voltage (ENC , ENC SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V PIN CONFIGURATIONS FULL-RATE CMOS OUTPUT MODE TOP VIEW ...
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... Differential Analog Input (Note Per Pin, 150Msps + – 0 < < Encode < PAR/SER < 0.625V < SENSE < 1.3V Figure 6 Test Circuit LTC2262-12 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C MIN TYP MAX –1 ±0 –0.4 ±0.1 0.4 l – ...
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... LTC2262-12 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SNR Signal-to-Noise Ratio www.datasheet4u.com SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio INTERNAL REFERENCE CHARACTERISTICS full operating temperature range, otherwise specifi ...
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... A CONDITIONS (Note 10) (Note 10) DC Input Sine Wave Input Sine Wave Input, OV =1. Input Sine Wave Input, OV =1.2V DD LTC2262-12 MIN TYP MAX l 1.3 l 0.6 l – 200 l –10 ...
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... LTC2262-12 POWER REQUIREMENTS range, otherwise specifi cations are at T SYMBOL PARAMETER LVDS Output Mode www.datasheet4u.com V Analog Supply Voltage DD OV Output Supply Voltage DD I Analog Supply Current VDD I Digital Supply Current OVDD (0V = 1.8V Power Dissipation DISS All Output Modes P Sleep Mode Power ...
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... Note 10: Recommended operating conditions. Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels – – – LTC2262-12 MIN TYP MAX 250 ...
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... LTC2262-12 TIMING DIAGRAMS www.datasheet4u.com ANALOG INPUT – ENC + ENC D0_1 • • • D10_11 OF + CLKOUT – CLKOUT ANALOG INPUT – ENC + ENC + D0_1 – D0_1 • • • + D10_11 – D10_11 + OF – CLKOUT – CLKOUT 8 Double Data Rate CMOS Output Mode Timing ...
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... OUTPUT CODE 226212 G01 LTC2262-12 t SCK LTC2262-12: 8k Point FFT, f –1dBFS, 150Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 3072 4096 FREQUENCY (MHz) 226212 G02 ...
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... INPUT LEVEL (dBFS) 226212 G10 = 70MHz LTC2262-12: 8k Point FFT –1dBFS, 150Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 60 70 ...
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... SCK. In the parallel programming mode (PAR/SER = V ), SDI can be used to power down the part. When SDI DD is low, the part operates normally. When SDI is high, the LTC2262-12 LTC2262-12: SNR vs Sample Rate and Digital Output Mode, 30MHz Sine Wave Input, –1dB 71 70 DDR CMOS ...
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... LTC2262-12 PIN FUNCTIONS part enters sleep mode. SDI can be driven with 1.8V to 3.3V logic. www.datasheet4u.com SDO (Pin 16): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1 ...
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... BUF SENSE APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2262- low power 12-bit 150Msps A/D converter that is powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially or single-ended for lower power consumption. The digital outputs can be CMOS, ...
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... A/D input at its optimal CM 50Ω 0.1μ 0.1μF 25Ω 1.8pF 25Ω – 50Ω 0.1μF 0.1μF 2.7nH + A IN LTC2262-12 0.1μF 25Ω T1 0.1μF 25Ω 2.7nH – T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE LTC2262-12 226212 F05 226212 F06 226212p ...
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... A/D. Reference The LTC2262-12 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE For a 1V input range using the external DD reference, connect SENSE to ground ...
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... V (up to 3.6V should have fast 0.1μF + ENC T1 1:4 100Ω 100Ω – ENC 0.1μF Figure 12. Sinusoidal Encode Drive 0.1μF + ENC PECL OR LTC2262-12 LVDS CLOCK 0.1μF – ENC 226212 F13 Figure 13. PECL or LVDS Encode Drive + threshold LTC2262-12 226212 F12 226212p ...
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... DIGITAL OUTPUTS Digital Output Modes The LTC2262-12 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system). The output mode is set by mode control register A3 (serial programming mode SCK (parallel programming mode) ...
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... CLKOUT signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2262-12 can also phase shift the CLKOUT – CLKOUT signals by serially programming mode con- trol register A2. The output clock can be shifted by 0° ...
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... CLKOUT OF D11/D0 D10/D0 • • • D2/D0 D1/D0 D0 226212 F15 LTC2262-12 PC BOARD FPGA CLKOUT OF D11/D0 D11 D10/D0 LTC2262-12 D10 • • D2/D0 • D2 D1/ Figure 16. Unrandomizing a Randomized Digital Output Signal 226212 F15 226212p 19 ...
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... Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2262-12 can be pro- grammed by either a parallel interface or a simple serial interface. The serial interface has more fl exibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes ...
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... To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero Power Down Control Bits LTC2262- PWROFF1 PWROFF0 226212p 21 ...
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... LTC2262-12 APPLICATIONS INFORMATION REGISTER A2: TIMING REGISTER (ADDRESS 02h www.datasheet4u.com X X Bits 7-4 Unused, Don’t Care Bits. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 CLKOUT Delay (As Shown in the Timing Diagrams CLKOUT+/CLKOUT– ...
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... HEAT TRANSFER Most of the heat generated by the LTC2262-12 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board ...
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... LTC2262-12 TYPICAL APPLICATIONS www.datasheet4u.com T2 MABAES0060 R9 10Ω • • ANALOG INPUT R10 10Ω R15 100Ω C12 C13 0.1μF 1μF 24 LTC2262 Evaluation Board Schematic SENSE R39 33.2Ω 1% R14 C51 1k 4.7pF R40 33.2Ω 1% C17 1μF C19 0.1μ SENSE V DD R27 10Ω ...
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... TYPICAL APPLICATIONS Silkscreen Top www.datasheet4u.com Inner Layer 2 GND 226212 TA03 226212 TA05 LTC2262-12 Top Side 226212 TA04 Inner Layer 3 226212 TA06 226212p 25 ...
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... LTC2262-12 TYPICAL APPLICATIONS Inner Layer 4 www.datasheet4u.com 26 226212 TA07 Bottom Side 226212 TA09 Inner Layer 5 Power 226212 TA08 226212p ...
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... LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0. 0.10 TYP 4.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2262- 0.115 TYP 39 40 0.40 ± 0. PIN 1 NOTCH R = 0.45 OR 0.35 45° CHAMFER 4.42 ±0.10 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.25 ± 0.05 0.50 BSC BOTTOM VIEW— ...
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... LTC2262-12 RELATED PARTS PART NUMBER DESCRIPTION LTC1993-2 High Speed Differential Op Amp www.datasheet4u.com LTC1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise LTC2204 16-Bit, 40Msps, 3.3V ADC LTC2205 16-Bit, 65Msps, 3 ...