LTC2262-12 Linear Dimensions Semiconductor, LTC2262-12 Datasheet - Page 12

• Manufacturer Part Number: LTC2262-12
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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LTC2262-12
PIN FUNCTIONS
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = V
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OV
with a 0.1μF ceramic capacitor.
V
Equal to V
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
V
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to V
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is
the MSB.
CLKOUT
CLKOUT
normally transition at the same time as the falling edge
of CLKOUT
relative to the digital outputs by programming the mode
control registers.
DNC (Pins 17, 18, 35): Do not connect these pins.
12
CM
REF
DD
DD
(Pin 38): Reference Voltage Output. Bypass to ground
(Pin 37): Common Mode Bias Output, Nominally
)
(Pin 26): Output Driver Supply. Bypass to ground
–
+
(Pin 28): Data Output Clock. The digital outputs
DD
(Pin 27): Inverted version of CLKOUT
DD
+
. The phase of CLKOUT
/2. V
selects the internal reference and a ±1V input
CM
should be used to bias the common
SENSE
.
+
DD
can also be delayed
), SDO is not used
+
.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8,
D10) appear when CLKOUT
D3, D5, D7, D9, D11) appear when CLKOUT
CLKOUT
CLKOUT
normally transition at the same time as the falling and ris-
ing edges of CLKOUT
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1
23/24, 29/30, 31/32, 33/34): Double Data Rate Digital
Outputs. Two data bits are multiplexed onto each differential
output pair. The even data bits (D0, D2, D4, D6, D8, D10)
appear when CLKOUT
D5, D7, D9, D11) appear when CLKOUT
CLKOUT
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT
CLKOUT
by programming the mode control registers.
OF
is high when an overfl ow or underfl ow has occurred.
DD
–
/OF
–
)
/D0_1
+
+
–
+
–
(Pins 35/36): Over/Under Flow Digital Output. OF
/CLKOUT
can also be delayed relative to the digital outputs
(Pin 28): Data Output Clock. The digital outputs
(Pin 27): Inverted version of CLKOUT
+
to D10_11
+
(Pins 27/28): Data Output Clock.
+
+
. The phase of CLKOUT
is low. The odd data bits (D1, D3,
–
/D10_11
+
is low. The odd data bits (D1,
+
(Pins 19/20, 21/22,
+
is high.
+
. The phase of
+
is high.
+
+
can also
.
226212p
+